Extension register bank mapping
NEON technology and VFP use the same extension register bank, which is distinct from the ARM register bank.
The extension register bank is a collection of registers which can be accessed as either 32-bit, 64-bit, or 128-bit registers, depending on whether the instruction is NEON or VFP.
The following figure shows the three views of the extension register bank, and the overlap between the different size registers. For example, the 128-bit register Q0 is an alias for two consecutive 64-bit registers D0 and D1, and is also an alias for four consecutive 32-bit registers S0, S1, S2, and S3. The 128-bit register Q8 is an alias for 2 consecutive 64-bit registers D16 and D17 but does not have an alias using the 32-bit Sn registers.
The figure applies to a VFP implementation with 32 double precision registers. The following versions of VFP use 16 double precision registers, D0-D15.
NEON technology uses 32 double precision registers, so if your processor implements one of the VFP versions in this list, it cannot also implement NEON technology.
The aliased views enable half-precision, single-precision, double-precision values, and NEON vectors to coexist in different non-overlapped registers at the same time.
You can also use the same overlapped registers to store half-precision, single-precision, and double-precision values, and NEON vectors at different times.
Do not attempt to use overlapped 32-bit and 64-bit, or 128-bit registers at the same time because it creates meaningless results.
Extension register bank
The mapping between the registers is as follows:
S<2n> maps to the least significant half of D<n>.
S<2n+1> maps to the most significant half of D<n>.
D<2n> maps to the least significant half of Q<n>.
D<2n+1> maps to the most significant half of Q<n>.
For example, you can access the least significant half of the elements of a vector in Q6 by referring to D12, and the most significant half of the elements by referring to D13.