Generate a PC-relative address in the destination register, for a label in the current area.
is an optional condition code.
is an optional instruction width specifier.
is the destination register to load.
is a PC-relative expression.
labelmust be within a limited distance of the current instruction.
ADR produces position-independent
code, because the assembler generates an instruction that adds or
subtracts a value to the PC.
to assemble a wider range of effective addresses.
label must evaluate to
an address in the same assembler area as the
If you use
ADR to generate a target
it is your responsibility to set the Thumb bit (bit 0) of the address
if the target contains Thumb instructions.
Offset range and architectures
The assembler calculates the offset from the PC for you. The assembler
generates an error if
is out of range.
The following table shows the possible offsets between the label and the current instruction:
Notes about the Architectures column
Entries in the Architectures column indicate that the instructions are available as follows:
All versions of the ARM architecture.
The ARMv6T2 and above architectures.
The ARMv4T, ARMv5T*, ARMv6*, and ARMv7 architectures.
ADR in Thumb
You can use the
.W width specifier to force
generate a 32-bit instruction in Thumb code.
generates a 32-bit instruction, even if the address can be generated
in a 16-bit instruction.
For forward references,
generates a 16-bit instruction in Thumb code, even if that results
in failure for an address that could be generated in a 32-bit Thumb
In Thumb code,
R cannot be
In ARM code,
R can be
SP is deprecated in ARMv6T2 and above.
Must be a multiple of 4.