Generate a register-relative address in the destination register, for a label defined in a storage map.
is an optional condition code.
is an optional instruction width specifier.
is the destination register to load.
is a symbol defined by the
labelspecifies an offset from the base register which is defined using the
labelmust be within a limited distance from the base register.
ADR generates code to easily access
named fields inside a storage map.
to assemble a wider range of effective addresses.
In Thumb code:
SPonly if the base register is
Offset range and architectures
The assembler calculates the offset from the base register for you. The
assembler generates an error if
is out of range.
The following table shows the possible offsets between the label and the current instruction:
Table 11-4 Register-relative offsets
Notes about the Architectures column
Entries in the Architectures column indicate that the instructions are available as follows:
All versions of the ARM architecture.
The ARMv6T2 and above architectures.
The ARMv4T, ARMv5T*, ARMv6*, and ARMv7 architectures.
ADR in Thumb
You can use the
.W width specifier to force
generate a 32-bit instruction in Thumb code.
generates a 32-bit instruction, even if the address can be generated
in a 16-bit instruction.
For forward references,
with base register SP, always generates a 16-bit instruction in
Thumb code, even if that results in failure for an address that
could be generated in a 32-bit Thumb
Must be a multiple of 4.