Signed saturating addition.
is an optional condition code.
is the destination register.
are the registers holding the operands.
QADD instruction adds the values in
. It saturates the result to the signed
range –231 ≤
x ≤ 231–1.
All values are treated as two’s complement signed integers by this instruction.
You cannot use PC for any operand.
You can use SP in ARM instructions but this is deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.
If saturation occurs, this instruction sets the Q flag. To
read the state of the Q flag, use an
This ARM instruction is available in ARMv6 and above, and E variants of ARMv5T.
This 32-bit Thumb instruction is available in ARMv6T2 and above. For the ARMv7-M architecture, it is only available in an ARMv7E-M implementation.
There is no 16-bit version of this instruction in Thumb.
QADD r0, r1, r9