Branch and change to Jazelle state.
is an optional condition code.
is not available on all forms of this instruction.
is a register containing an address to branch to.
BXJ instruction causes a branch
to the address contained in
changes the instruction set state to Jazelle.
Instruction availability and branch ranges
The following table shows the
that are available in ARM and Thumb state. Instructions that are
not shown in this table are not available. Notes in brackets show
the first architecture version where the instruction is available.
Table 11-9 BXJ instruction availability and range
|Instruction||ARM||Thumb, 16-bit encoding||Thumb, 32-bit encoding|
||Available||(5J, 6)||-||Available||(All T2 except ARMv7-M)|
You can use SP for
R in the
instruction but this is deprecated in ARMv6T2 and above.
You cannot use SP in the
BXJ instruction does not change
See the preceding table for details of availability of the
BXJ instruction in