Change Processor State.
is one of:
Interrupt or abort enable.
Interrupt or abort disable.
is a sequence of one or more of:
Enables or disables imprecise aborts.
Enables or disables IRQ interrupts.
Enables or disables FIQ interrupts.
specifies the number of the mode to change to.
Changes one or more of the mode, A, I, and F bits in the CPSR, without changing the other CPSR bits.
CPS is only permitted in privileged software execution, and has no effect
in User mode.
CPS cannot be conditional, and is not permitted in an IT block.
This instruction does not change the condition flags.
The following forms of these instructions are available in Thumb code, and are 16-bit instructions:
You cannot specify a mode change in a 16-bit Thumb instruction.
This ARM instruction is available in ARMv6 and above.
This 32-bit Thumb instruction are available in ARMv6T2 and above.
This 16-bit Thumb instruction is available in T variants of ARMv6 and above.
CPSIE if ; Enable IRQ and FIQ interrupts. CPSID A ; Disable imprecise aborts. CPSID ai, #17 ; Disable imprecise aborts and interrupts, and enter FIQ mode. CPS #16 ; Enter User mode.