Signed halving parallel byte-wise addition.
is an optional condition code.
is the destination register.
are the ARM registers holding the operands.
This instruction performs four signed integer additions on the corresponding bytes of the operands, halves the results, and writes the results into the corresponding bytes of the destination. This cannot cause overflow.
You cannot use PC for any register.
You can use SP in ARM instructions but this is deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.
This instruction does not affect the N, Z, C, V, Q, or GE flags.
This ARM instruction is available in ARMv6 and above.
This 32-bit Thumb instruction is available in ARMv6T2 and above. For the ARMv7-M architecture, it is only available in an ARMv7E-M implementation.
There is no 16-bit version of this instruction in Thumb.