Dual 16-bit Signed Multiply with Subtraction of products and 64-bit accumulation.
is an optional parameter. If X is present, the most and least significant halfwords of the second operand are exchanged before the multiplications occur.
is an optional condition code.
are the destination registers for the 64-bit result. They also hold the 64-bit accumulate operand.
RdLomust be different registers.
are the registers holding the operands.
SMLSLD multiplies the bottom halfword of
Rn with the bottom
Rm, and the top halfword of
Rn with the
top halfword of
Rm. It then subtracts the second product from the first,
adds the difference to the value in
stores the result to
You cannot use PC for any register.
You can use SP in ARM instructions but this is deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.
This instruction does not change the flags.
This ARM instruction is available in ARMv6 and above.
This 32-bit Thumb instruction is available in ARMv6T2 and above. For the ARMv7-M architecture, it is only available in an ARMv7E-M implementation.
There is no 16-bit version of this instruction in Thumb.
SMLSLD r3, r0, r5, r1