Signed Long Multiply, with 32-bit operands and 64-bit result.
is an optional suffix available in ARM state only. If S is specified, the condition flags are updated on the result of the operation.
is an optional condition code.
are the destination registers.
RdHimust be different registers
are ARM registers holding the operands.
SMULL instruction interprets the values from
Rm as twoâ€™s complement signed integers. It multiplies these integers
and places the least significant 32 bits of the result in
RdLo, and the
most significant 32 bits of the result in
Rn must be different from
architectures before ARMv6.
You cannot use PC for any register.
You can use SP in ARM instructions but this is deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.
If S is specified, this instruction:
Updates the N and Z flags according to the result.
Does not affect the C or V flags.
This ARM instruction is available in all versions of the ARM architecture.
This 32-bit Thumb instruction is available in ARMv6T2 and above.
There is no 16-bit version of this instruction in Thumb.