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Pseudo-instructions

The ARM assembler supports a number of pseudo-instructions that are translated into the appropriate combination of ARM, or Thumb instructions at assembly time.

The pseudo-instructions are described in the following sections:

  • ADRL pseudo-instruction

    Load a PC-relative or register-relative address into a register (medium range, position independent)

  • MOV32 pseudo--instruction

    Load a register with a 32-bit immediate value or an address (unlimited range, but not position independent). Available for ARMv6T2 and above only.

  • LDR pseudo-instruction

    Load a register with a 32-bit immediate value or an address (unlimited range, but not position independent). Available for all ARM architectures.

  • UND pseudo-instruction

    Generate an architecturally undefined instruction. Available for all ARM architectures.