ADR generates a PC-relative address in the destination
register, for a label in the current area.
is an optional condition code.
is an optional instruction width specifier.
is the destination register to load.
is a PC-relative expression.
must be within a limited distance of the current instruction.
ADR produces position-independent code, because
the assembler generates an instruction that adds or subtracts a
value to the PC.
ADRL pseudo-instruction to assemble a
wider range of effective addresses.
evaluate to an address in the same assembler area as the
If you use
ADR to generate a target for a
it is your responsibility to set the Thumb bit (bit 0) of the address
if the target contains Thumb instructions.
The assembler calculates the offset from the PC for you. The
assembler generates an error if
out of range.
Table 6 shows the possible offsets between the label and the current instruction.
|ARM ||See Operand2 as a constant||All|
|32-bit Thumb ||+/- 4095||T2|
|16-bit Thumb ||0-1020 [c]||T|
[a] Entries in the Architectures column indicate that the instructions are available as follows:
[b] Rd must be in the range R0-R7.
[c] Must be a multiple of 4.
You can use the
.W width specifier to force
generate a 32-bit instruction in Thumb code.
generates a 32-bit instruction, even if the address can be generated
in a 16-bit instruction.
For forward references,
generates a 16-bit instruction in Thumb code, even if that results
in failure for an address that could be generated in a 32-bit Thumb
In Thumb code,
In ARM code,
SP but use of
deprecated in ARMv6T2 and above.