ADR generates a register-relative address in
the destination register, for a label defined in a storage map.
is an optional condition code.
is an optional instruction width specifier.
is the destination register to load.
is a symbol defined by the FIELD directive.
labelspecifies an offset from the base register which is defined using the MAP directive.
must be within a limited distance from the base register.
ADR generates code to easily access named fields
inside a storage map.
ADRL pseudo-instruction to assemble a
wider range of effective addresses.
The assembler calculates the offset from the base register
for you. The assembler generates an error if
out of range.
Table 7 shows the possible offsets between the label and the current instruction.
|ARM ||See Operand2 as a constant||All|
|32-bit Thumb ||+/- 4095||T2|
|16-bit Thumb ||0-1020 [c]||T|
[a] Entries in the Architectures column indicate that the instructions are available as follows:
[c] Must be a multiple of 4.
You can use the
.W width specifier to force
generate a 32-bit instruction in Thumb code.
generates a 32-bit instruction, even if the address can be generated
in a 16-bit instruction.
For forward references,
with base register SP, always generates a 16-bit instruction in
Thumb code, even if that results in failure for an address that
could be generated in a 32-bit Thumb