Load a PC-relative or register-relative address into a register.
It is similar to the ADR instruction. ADRL can
load a wider range of addresses than ADR because it
generates two data processing instructions.
Note
When assembling Thumb instructions, ADRL is only
available in ARMv6T2 and later.
ADRL{cond}Rd,label
where:
condis an optional condition code.
Rdis the register to load.
labelis a PC-relative or register-relative expression.
ADRL always assembles to two 32-bit instructions.
Even if the address can be reached in a single instruction, a second,
redundant instruction is produced.
If the assembler cannot construct the address in two instructions,
it generates an error message and the assembly fails. You can use
the LDR pseudo-instruction for loading a wider range
of addresses.
ADRL produces position-independent code, because
the address is PC-relative or register-relative.
If labelADRL pseudo-instruction.
If you use ADRL to generate a target for a BX or BLX instruction,
it is your responsibility to set the Thumb bit (bit 0) of the address
if the target contains Thumb instructions.
The available range depends on the instruction set in use:
- ARM
The range of the instruction is any value that can be generated by two
ADDor twoSUBinstructions. That is, any value that can be produced by the addition of two values, each of which is 8 bits rotated right by any even number of bits within a 32-bit word. See Operand2 as a constant for more information.- 32-bit Thumb
±1MB bytes to a byte, halfword, or word-aligned address.
- 16-bit Thumb
ADRLis not available.
The given range is relative to a point four bytes (in Thumb code) or two words (in ARM code) after the address of the current instruction.
- Concepts
Using the Assembler:
- Reference
- Other information