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B, BL, BX, BLX, and BXJ

Branch, Branch with Link, Branch and exchange instruction set, Branch with Link and exchange instruction set, Branch and change to Jazelle state.


op1{cond}{.W} label
op2{cond} Rm



is one of:




Branch with link.


Branch with link, and exchange instruction set.


is one of:


Branch and exchange instruction set.


Branch with link, and exchange instruction set.


Branch, and change to Jazelle execution.


is an optional condition code. cond is not available on all forms of this instruction.


is an optional instruction width specifier to force the use of a 32-bit B instruction in 32-bit Thumb.


is a PC-relative expression.


is a register containing an address to branch to.


All these instructions cause a branch to label, or to the address contained in Rm. In addition:

  • The BL and BLX instructions copy the address of the next instruction into LR (R14, the link register).

  • The BX and BLX instructions can change the processor state from ARM to Thumb, or from Thumb to ARM.

    BLX label always changes the state.

    BX Rm and BLX Rm derive the target state from bit[0] of Rm:

    • if bit[0] of Rm is 0, the processor changes to, or remains in, ARM state

    • if bit[0] of Rm is 1, the processor changes to, or remains in, Thumb state.

  • The BXJ instruction changes the processor state to Jazelle.

Instruction availability and branch ranges

Table 8 shows the instructions that are available in ARM and Thumb state. Instructions that are not shown in this table are not available. Notes in brackets show the first architecture version where the instruction is available.

Table 8. Branch instruction availability and range
InstructionARM 16-bit Thumb32-bit Thumb
B label±32MB(All)±2KB(All T)±16MB[a](All T2)
B{cond} label±32MB(All)-252 to +258(All T)±1MBa(All T2)
BL label±32MB(All)±4MB [b](All T)±16MB(All T2)
BL{cond} label±32MB(All)- --
BX Rm [c]Available(4T, 5)Available(All T)Use 16-bit(All T2)
BX{cond} Rm [c]Available(4T, 5)- --
BLX label±32MB(5)±4MB [b](5T)±16MB(All T2 except ARMv7-M)
BLX RmAvailable(5)Available(5T)Use 16-bit(All T2)
BLX{cond} RmAvailable(5)- --
BXJ RmAvailable(5J, 6)- Available(All T2 except ARMv7-M)
BXJ{cond} RmAvailable(5J, 6)- --

[a] Use .W to instruct the assembler to use this 32-bit instruction.

[b] This is an instruction pair.

[c] The assembler accepts BX{cond} Rm for code assembled for ARMv4 and converts it to MOV{cond} PC, Rm at link time, unless objects targeted for ARMv4T are present.

Extending branch ranges

Machine-level B and BL instructions have restricted ranges from the address of the current instruction. However, you can use these instructions even if label is out of range. Often you do not know where the linker places label. When necessary, the linker adds code to enable longer branches. The added code is called a veneer.

B in Thumb

You can use the .W width specifier to force B to generate a 32-bit instruction in Thumb code.

B.W always generates a 32-bit instruction, even if the target could be reached using a 16-bit instruction.

For forward references, B without .W always generates a 16-bit instruction in Thumb code, even if that results in failure for a target that could be reached using a 32-bit Thumb instruction.

BX, BLX, and BXJ in ThumbEE

These instructions can be used as branches in ThumbEE code, but cannot be used to change state. You cannot use the op{cond} label form of these instructions in ThumbEE. In the register form, bit[0] of Rm must be 1, and execution continues at the target address in ThumbEE state.


BXJ behaves like BX in ThumbEE.

Register restrictions

You can use PC for Rm in the ARM BX instruction, but this is deprecated in ARMv6T2 and above. You cannot use PC in other ARM instructions.

You can use PC for Rm in the Thumb BX instruction. You cannot use PC in other Thumb instructions.

You can use SP for Rm in these ARM instructions but these are deprecated in ARMv6T2 and above.

You can use SP for Rm in the Thumb BX and BLX instructions, but these are deprecated. You cannot use SP in the other Thumb instructions.

Condition flags

These instructions do not change the flags.


See Table 8 for details of availability of these instructions in each architecture.


    B       loopA
    BLE     ng+8
    BL      subC
    BLLT    rtX
    BEQ     {PC}+4  ; #0x8004

See also

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