Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.
op
{type
}{cond
}Rt
, [Rn
{, #offset
}] ; immediate offset
op
{type
}{cond
}Rt
, [Rn
, #offset
]! ; pre-indexed
op
{type
}{cond
}Rt
, [Rn
], #offset
; post-indexed
op
D{cond
}Rt
,Rt2
, [Rn
{, #offset
}] ; immediate offset, doubleword
op
D{cond
}Rt
,Rt2
, [Rn
, #offset
]! ; pre-indexed, doubleword
op
D{cond
}Rt
,Rt2
, [Rn
], #offset
; post-indexed, doubleword
where:
op
can be either:
LDR
Load Register
STR
Store Register.
type
can be any one of:
B
unsigned Byte (Zero extend to 32 bits on loads.)
SB
signed Byte (
LDR
only. Sign extend to 32 bits.)H
unsigned Halfword (Zero extend to 32 bits on loads.)
SH
signed Halfword (
LDR
only. Sign extend to 32 bits.)-
omitted, for Word.
cond
is an optional condition code.
Rt
is the register to load or store.
Rn
is the register on which the memory address is based.
offset
is an offset. If
is omitted, the address is the contents ofoffset
.Rn
Rt2
is the additional register to load or store for doubleword operations.
Not all options are available in every instruction set and architecture.
Table 9 shows the ranges of offsets and availability of these instructions.
Instruction | Immediate offset | Pre-indexed | Post-indexed | Arch.[a] |
---|---|---|---|---|
ARM, word or byte [b] | -4095 to 4095 | -4095 to 4095 | -4095 to 4095 | All |
ARM, signed byte, halfword, or signed halfword | -255 to 255 | -255 to 255 | -255 to 255 | All |
ARM, doubleword | -255 to 255 | -255 to 255 | -255 to 255 | 5E |
32-bit Thumb, word, halfword, signed halfword, byte, or signed byte [b] | -255 to 4095 | -255 to 255 | -255 to 255 | T2 |
32-bit Thumb, doubleword | -1020 to 1020 [d] | -1020 to 1020 [d] | -1020 to 1020 [d] | T2 |
16-bit Thumb, word [c] | 0 to 124 [d] | Not available | Not available | T |
16-bit Thumb, unsigned halfword [c] | 0 to 62 [e] | Not available | Not available | T |
16-bit Thumb, unsigned byte [c] | 0 to 31 | Not available | Not available | T |
16-bit Thumb, word, Rn is
SP [f] | 0 to 1020 [d] | Not available | Not available | T |
16-bit ThumbEE, word [c] | -28 to 124 [d] | Not available | Not available | EE |
16-bit ThumbEE, word, Rn is R9 [f] | 0 to 252 [d] | Not available | Not available | EE |
16-bit ThumbEE, word, Rn is R10 [f] | 0 to 124 [d] | Not available | Not available | EE |
[a] Entries in the Architecture column indicate that the instructions are available as follows:
[b] For word loads, Rt can be the PC. A load to the PC causes a branch to the address loaded. In ARMv4, bits[1:0] of the address loaded must be 0b00. In ARMv5T and above, bits[1:0] must not be 0b10, and if bit[0] is 1, execution continues in Thumb state, otherwise execution continues in ARM state. [c] Rt and Rn must be in the range R0-R7. [d] Must be divisible by 4. [e] Must be divisible by 2. [f] Rt must be in the range R0-R7. |
R
must be different
from n
R
in the pre-index
and post-index forms.t2
For Thumb instructions, you must not specify SP or PC for
either
or Rt
.Rt2
For ARM instructions:
must be an even-numbered registerRt
must not be LRRt
it is strongly recommended that you do not use
R12
forRt
must beRt2
R(
t
+ 1).
In ARM instructions:
You can use PC for
R
int
LDR
word instructions and PC forR
inn
LDR
instructions.You can use PC for
R
int
STR
word instructions and PC forR
inn
STR
instructions with immediate offset syntax (that is the forms that do not writeback to theR
). However, these are deprecated in ARMv6T2 and above.n
Other uses of PC are not permitted in these ARM instructions.
In Thumb instructions you can use PC for R
in t
LDR
word
instructions and PC for R
in n
LDR
instructions.
Other uses of PC in these Thumb instructions are not permitted.
You can use SP for R
. n
In ARM, you can use SP for R
in
word instructions. You can use SP for t
R
in
non-word instructions in ARM code but this is deprecated in ARMv6T2
and above.t
In Thumb, you can use SP for R
in
word instructions only. All other use of SP for t
R
in
these instructions are not permitted in Thumb code.t
LDR r8,[r10] ; loads R8 from the address in R10. LDRNE r2,[r5,#960]! ; (conditionally) loads R2 from a word ; 960 bytes above the address in R5, and ; increments R5 by 960. STR r2,[r9,#consta-struc] ; consta-struc is an expression evaluating ; to a constant in the range 0-4095.