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MRC, MRC2, MRRC and MRRC2

Move to ARM Register or Registers from Coprocessor.

Depending on the coprocessor, you might be able to specify various operations in addition.

Syntax

op1{cond} coproc, #opcode1, Rt, CRn, CRm{, #opcode2}
op2{cond} coproc, #opcode3, Rt, Rt2, CRm

where:

op1

is either MRC or MRC2.

op2

is either MRRC or MRRC2.

cond

is an optional condition code. In ARM code, cond is not permitted for MRC2 or MRRC2.

coproc

is the name of the coprocessor the instruction is for. The standard name is pn, where n is an integer in the range 0 to 15.

opcode1

is a 3-bit coprocessor-specific opcode.

opcode2

is an optional 3-bit coprocessor-specific opcode.

opcode3

is a 4-bit coprocessor-specific opcode.

Rt, Rt2

are ARM destination registers. Rt and Rt2 must not be PC.

In MRC and MRC2, Rt can be APSR_nzcv. This means that the coprocessor executes an instruction that changes the value of the condition code flags in the APSR.

CRn, CRm

are coprocessor registers.

Usage

The use of these instructions depends on the coprocessor. See the coprocessor documentation for details.

Architectures

The MRC ARM instruction is available in all versions of the ARM architecture.

The MRC2 ARM instruction is available in ARMv5T and above.

The MRRC ARM instruction is available in ARMv6 and above, and E variants of ARMv5T.

The MRRC2 ARM instruction is available in ARMv6 and above.

These 32-bit Thumb instructions are available in ARMv6T2 and above.

There are no 16-bit Thumb versions of these instructions.

See also

Reference
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