Move the contents of a PSR to a general-purpose register.
is an optional condition code.
is the destination register.
is one of:
on any processor, in any mode.
deprecated synonym for APSR and for use in Debug state, on any processor except ARMv7-M and ARMv6-M.
on any processor except ARMv7-M and ARMv6-M, in privileged software execution only.
on ARMv7-M and ARMv6-M processors only.
can be any of:
MRS in combination with
part of a read-modify-write sequence for updating a PSR, for example
to change processor mode, or to clear the Q flag.
In process swap code, the programmers’ model state of the
process being swapped out must be saved, including relevant PSR
contents. Similarly, the state of the process being swapped in must
also be restored. These operations make use of
MSR instruction sequences.
You must not attempt to access the SPSR when the processor is in User or System mode. This is your responsibility. The assembler cannot warn you about this, because it has no information about the processor mode at execution time.
If you attempt to access the SPSR when the processor is in User or System mode, the result is unpredictable.
The CPSR endianness bit (E) can be read in any privileged software execution.
The CPSR execution state bits, other than the E bit, can only be read when the processor is in Debug state, halting debug-mode. Otherwise, the execution state bits in the CPSR read as zero.
The condition flags can be read in any mode on any processor. Use APSR if you are only interested in accessing the condition code flags in User mode.
R is PC
in ARM instructions, the result is unpredictable.
You can use SP for
ARM instructions but this is deprecated in ARMv6T2 and above.
R is PC
or SP in Thumb instructions, the result is unpredictable.
This ARM instruction is available in all versions of the ARM architecture.
These 32-bit Thumb instructions are available in ARMv6T2 and above.
There is no 16-bit Thumb version of this instruction.