Preload Data and Preload Instruction. The processor can signal the memory system that a data or instruction load from an address is likely in the near future.
can be one of:
Data address with intention to write
DWif the syntax specifies
is an optional condition code.
is permitted only in 32-bit Thumb code, using a preceding
ITinstruction. This is an unconditional instruction in ARM code and you must not use
is the register on which the memory address is based.
is an immediate offset. If offset is omitted, the address is the value in
is a register containing a value to be used as the offset.
is an optional shift.
is a PC-relative expression.
The offset is applied to the value in
the preload takes place. The result is used as the memory address
for the preload. The range of offsets permitted is:
-4095 to +4095 for ARM instructions
-255 to +4095 for 32-bit Thumb instructions, when
is not PC.
-4095 to +4095 for 32-bit Thumb instructions, when
The assembler calculates the offset from the PC for you. The
assembler generates an error if
out of range.
In ARM code, the value in
added to or subtracted from the value in
In 32-bit Thumb code, the value in
only be added to the value in
The result used as the memory address for the preload.
The range of shifts permitted is:
LSL#0 to #3 for 32-bit Thumb instructions
Any one of the following for ARM instructions:
LSL#0 to #31
LSR#1 to #32
ASR#1 to #32
ROR#1 to #31
be PC. For Thumb instructions
also not be SP.
be PC for Thumb instructions of the syntax
PLD is available in ARMv5TE and above.
PLD is available in ARMv6T2 and
PLDW is available only in ARMv7 and above that
implement the Multiprocessing Extensions.
PLI is available only in ARMv7 and above.
There are no 16-bit Thumb
These are hint instructions, and their implementation is optional.
If they are not implemented, they execute as