is an optional condition code.
is an expression evaluating to an integer in the range:
0 to 224-1 (a 24-bit value) in an ARM instruction
0-255 (an 8-bit value) in a 16-bit Thumb instruction.
SVC instruction causes an exception. This
means that the processor mode changes to Supervisor, the CPSR is
saved to the Supervisor mode SPSR, and execution branches to the SVC
by the processor. However, it can be retrieved by the exception
handler to determine what service is being requested.
SVC was called
SWI in earlier versions
of the ARM assembly language.
SWI instructions disassemble
SVC, with a comment to say that this was formerly
This ARM instruction is available in all versions of the ARM architecture.
This 16-bit Thumb instruction is available in all T variants of the ARM architecture.
There is no 32-bit Thumb version of this instruction.