Test bits and Test Equivalence.
TST
{cond
}Rn
,Operand2
TEQ
{cond
}Rn
,Operand2
where:
cond
is an optional condition code.
Rn
is the ARM register holding the first operand.
Operand2
is a flexible second operand.
These instructions test the value in a register against
.
They update the condition flags on the result, but do not place
the result in any register.Operand2
The TST
instruction performs a bitwise AND operation
on the value in
and
the value of Rn
.
This is the same as an Operand2
ANDS
instruction, except that
the result is discarded.
The TEQ
instruction performs a bitwise Exclusive
OR operation on the value in
and
the value of Rn
.
This is the same as a Operand2
EORS
instruction, except that
the result is discarded.
Use the TEQ
instruction to test if two values
are equal, without affecting the V or C flags (as CMP
does).
TEQ
is also useful for testing the sign of a
value. After the comparison, the N flag is the logical Exclusive
OR of the sign bits of the two operands.
In these Thumb instructions, you cannot use SP or PC for
or Rn
Operand2.
In these ARM instructions, use of SP or PC is deprecated in ARMv6T2 and above.
For ARM instructions:
if you use PC (
R15
) as
, the value used is the address of the instruction plus 8Rn
you cannot use PC for any operand in any data processing instruction that has a register-controlled shift.
These instructions:
update the N and Z flags according to the result
can update the C flag during the calculation of
Operand2
do not affect the V flag.
The following form of the TST
instruction is
available in Thumb code, and is a 16-bit instruction:
TST
Rn
,Rm
andRn
must both be Lo registers.Rm
These ARM instructions are available in all architectures that support the ARM instruction set.
The TST
Thumb instruction is available in all
architectures that support the Thumb instruction set.
The TEQ
Thumb instruction is available in ARMv6T2
and above.
- Concepts
- Reference