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This option instructs the assembler to fault LDM and STM instructions with a large number of registers. Use of this option is deprecated.

This option faults LDM instructions if the maximum number of registers transferred exceeds:

  • 5, for LDMs that do not load the PC

  • 4, for LDMs that load the PC.

This option faults STM instructions if the maximum number of registers transferred exceeds 5.

Avoiding large multiple register transfers can reduce interrupt latency on ARM systems that:

  • do not have a cache or a write buffer (for example, a cacheless ARM7TDMI)

  • use zero wait-state, 32-bit memory.

Also, avoiding large multiple register transfers:

  • always increases code size.

  • has no significant benefit for cached systems or processors with a write buffer.

  • has no benefit for systems without zero wait-state memory, or for systems with slow peripheral devices. Interrupt latency in such systems is determined by the number of cycles required for the slowest memory or peripheral access. This is typically much greater than the latency introduced by multiple register transfers.

See also

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