Pop registers off a full descending stack.
This instruction causes a branch to the address popped off the stack into the PC. This is usually a return from a subroutine, where the LR was pushed onto the stack at the start of the subroutine.
In ARMv5T and above:
bits[1:0] must not be 0b10
if bit is 1, execution continues in Thumb state
if bit is 0, execution continues in ARM state.
In ARMv4, bits[1:0] of the address loaded must be 0b00.
A subset of these instructions are available in the Thumb instruction set.
The following restriction applies to the 16-bit
can only include the Lo registers and the PC.
The following restrictions apply to the 32-bit
must not include the SP
can include either the LR or the PC, but not both.