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ARM and Thumb instruction summary

Table 4 gives an overview of the instructions available in the ARM and Thumb instruction sets. Use it to locate individual instructions and pseudo-instructions.

Table 4. Location of instructions
MnemonicBrief descriptionSeeArch. [a]
ADCAdd with CarryADCAll
ADDAddADDAll
ADRLoad program or register-relative address (short range)ADR (PC-relative)All
ADRL pseudo-instructionLoad program or register-relative address (medium range)ADRL pseudo-instructionx6M
ANDLogical ANDANDAll
ASRArithmetic Shift RightASRAll
BBranchBAll
BFCBit Field ClearBFC T2
BFIBit Field InsertBFIT2
BICBit ClearBICAll
BKPTBreakpointBKPT5
BLBranch with LinkBLAll
BLXBranch with Link, change instruction setBLXT
BXBranch, change instruction setBXT
BXJBranch, change to Jazelle®BXJJ, x7M
CBZ, CBNZCompare and Branch if {Non}ZeroCBZ and CBNZT2
CDPCoprocessor Data Processing operationCDP and CDP2x6M
CDP2Coprocessor Data Processing operationCDP and CDP25, x6M
CLREXClear ExclusiveCLREXK, x6M
CLZCount leading zerosCLZ5, x6M
CMN, CMPCompare Negative, CompareCMP and CMNAll
CPSChange Processor StateCPS6
CPY pseudo-instructionCopyCPY pseudo-instruction6
DBGDebugDBG7
DMBData Memory BarrierDMB7, 6M
DSBData Synchronization BarrierDSB7, 6M
EORExclusive OREORAll
ERETException ReturnERET7VE
ISBInstruction Synchronization BarrierISB7, 6M
ITIf-ThenITT2
LDCLoad CoprocessorLDC and LDC2x6M
LDC2Load CoprocessorLDC and LDC25, x6M
LDMLoad Multiple registersLDMAll
LDRLoad Register with wordMemory access instructionsAll
LDR pseudo-instructionLoad Register pseudo-instructionLDR pseudo-instructionAll
LDRBLoad Register with byteMemory access instructionsAll
LDRBTLoad Register with byte, user modeMemory access instructionsx6M
LDRDLoad Registers with two wordsMemory access instructions5E, x6M
LDREXLoad Register ExclusiveLDREX6, x6M
LDREXB, LDREXHLoad Register Exclusive Byte, HalfwordLDREXK, x6M
LDREXDLoad Register Exclusive DoublewordLDREXK, x7M
LDRHLoad Register with halfwordMemory access instructionsAll
LDRHTLoad Register with halfword, user modeMemory access instructionsT2
LDRSBLoad Register with signed byteMemory access instructionsAll
LDRSBTLoad Register with signed byte, user modeMemory access instructionsT2
LDRSHLoad Register with signed halfwordMemory access instructionsAll
LDRSHTLoad Register with signed halfword, user modeMemory access instructionsT2
LDRTLoad Register with word, user modeMemory access instructionsx6M
LSLLogical Shift LeftLSLAll
LSRLogical Shift RightLSRAll
MARMove from Registers to 40-bit AccumulatorMARXScale
MCRMove from Register to CoprocessorMCR and MCR2x6M
MCR2Move from Register to CoprocessorMCR and MCR25, x6M
MCRRMove from Registers to CoprocessorMCRR and MCRR25E, x6M
MCRR2Move from Registers to CoprocessorMCRR and MCRR26, x6M
MIA, MIAPH, MIAxyMultiply with Internal 40-bit AccumulateMIA, MIAPH, and MIAxyXScale
MLAMultiply AccumulateMLAx6M
MLSMultiply and SubtractMLST2
MOVMoveMOVAll
MOVTMove TopMOVTT2
MOV32 pseudo-instructionMove 32-bit immediate to registerMOV32 pseudo-instructionT2
MRAMove from 40-bit Accumulator to RegistersMRAXScale
MRCMove from Coprocessor to RegisterMRC and MRC2x6M
MRC2Move from Coprocessor to RegisterMRC and MRC25, x6M
MRRCMove from Coprocessor to RegistersMRRC and MRRC25E, x6M
MRRC2Move from Coprocessor to RegistersMRRC and MRRC26, x6M
MRSMove from PSR to registerMRS (PSR to general-purpose register)All
MRSMove from system Coprocessor to RegisterMRS (system coprocessor register to ARM register)7A, 7R
MSRMove from register to PSRMSR (general-purpose register to PSR)All
MSRMove from Register to system CoprocessorMSR (ARM register to system coprocessor register)7A, 7R
MULMultiplyMULAll
MVNMove NotMVNAll
NEG pseudo-instructionNegateNEG pseudo-instructionAll
NOPNo OperationNOPAll
ORNLogical OR NOTORN (Thumb only)T2
ORRLogical ORORRAll
PKHBT, PKHTBPack HalfwordsPKHBT and PKHTB6, 7EM
PLDPreload DataPLD, PLDW, and PLI5E, x6M
PLDWPreload Data with intent to WritePLD, PLDW, and PLI7MP
PLIPreload InstructionPLD, PLDW, and PLI7
POPPOP registers from stackPOPAll
PUSHPUSH registers to stackPUSHAll
QADDSigned saturating AddQADD5E, 7EM
QDADDSigned saturating Double and AddQDADD5E, 7EM
QDSUBSigned saturating Double and SubtractQDSUB5E, 7EM
QSUBSigned saturating SubtractQSUB5E, 7EM
QADD8, QADD16, QASX, QSUB8, QSUB16, QSAXParallel signed Saturating ArithmeticParallel add and subtract6, 7EM
RBITReverse BitsRBITT2
REVReverse byte order in a wordREV6
REV16Reverse byte order in two halfwordsREV6
REVSHReverse byte order in a halfword and sign extendREV6
RFEReturn From ExceptionRFET2, x7M
RORRotate Right RegisterRORAll
RRXRotate Right with ExtendRRXx6M
RSBReverse SubtractRSBAll
RSCReverse Subtract with CarryRSCx7M
SADD8, SADD16, SASXParallel signed arithmeticParallel add and subtract6, 7EM
SBCSubtract with CarrySBCAll
SBFXSigned Bit Field eXtractSBFXT2
SDIVSigned divideSDIV7M, 7R
SELSelect bytes according to APSR GE flagsSEL6, 7EM
SETENDSet Endianness for memory accessesSETEND6, x7M
SEVSet EventSEVK, 6M
SHADD8, SHADD16, SHASX, SHSUB8, SHSUB16, SHSAXParallel signed Halving arithmeticParallel add and subtract6, 7EM
SMCSecure Monitor CallSMCZ
SMLAxySigned Multiply with Accumulate (32 <= 16 x 16  +  32)SMLAxy5E, 7EM
SMLADDual Signed Multiply Accumulate SMLAD 6, 7EM
 (32 <= 32 + 16 x 16 + 16 x 16)  
SMLALSigned Multiply Accumulate (64 <= 64 + 32 x 32)SMLALx6M
SMLALxySigned Multiply Accumulate (64 <= 64 + 16 x 16) SMLALxy5E, 7EM
SMLALDDual Signed Multiply Accumulate LongSMLALD6, 7EM
 (64 <= 64 + 16 x 16 + 16 x 16)  
SMLAWySigned Multiply with Accumulate (32 <= 32 x 16  +  32)SMLAWy5E, 7EM
SMLSDDual Signed Multiply Subtract AccumulateSMLSD6, 7EM
 (32 <= 32 + 16 x 16 - 16 x 16)  
SMLSLDDual Signed Multiply Subtract Accumulate LongSMLSLD6, 7EM
 (64 <= 64 + 16 x 16 - 16 x 16)  
SMMLASigned top word Multiply with Accumulate (32 <= TopWord(32 x 32  +  32))SMMLA6, 7EM
SMMLSSigned top word Multiply with Subtract (32 <= TopWord(32  -  32 x 32))SMMLS6, 7EM
SMMULSigned top word Multiply (32 <= TopWord(32 x 32))SMMUL6, 7EM
SMUAD, SMUSDDual Signed Multiply, and Add or Subtract productsSMUAD6, 7EM
SMULxySigned Multiply (32 <= 16 x 16)SMULxy5E, 7EM
SMULLSigned Multiply (64 <= 32 x 32)SMULLx6M
SMULWySigned Multiply (32 <= 32 x 16)SMULWy5E, 7EM
SRSStore Return StateSRST2, x7M
SSATSigned SaturateSSAT6, x6M
SSAT16Signed Saturate, parallel halfwordsSSAT166, 7EM
SSUB8, SSUB16, SSAXParallel signed arithmeticParallel add and subtract6, 7EM
STCStore CoprocessorSTC and STC2x6M
STC2Store CoprocessorSTC and STC25, x6M
STMStore Multiple registersSTMAll
STRStore Register with wordMemory access instructionsAll
STRBStore Register with byteMemory access instructionsAll
STRBTStore Register with byte, user modeMemory access instructionsx6M
STRDStore Registers with two wordsMemory access instructions5E, x6M
STREXStore Register ExclusiveSTREX6, x6M
STREXB, STREXHStore Register Exclusive Byte, HalfwordSTREXK, x6M
STREXDStore Register Exclusive DoublewordSTREXK, x7M
STRHStore Register with halfwordMemory access instructionsAll
STRHTStore Register with halfword, user modeMemory access instructionsT2
STRTStore Register with word, user modeMemory access instructionsx6M
SUBSubtractSUBAll
SUBS pc, lrException return, no stackSUBS pc, lrT2, x7M
SVC (formerly SWI)SuperVisor CallSVCAll
SWP, SWPBSwap registers and memory (ARM only)SWP and SWPBAll, x7M
SXTABSign extend Byte, with AdditionSXTAB6, 7EM
SXTAB16Sign extend two Bytes, with AdditionSXTAB166, 7EM
SXTAHSign extend Halfword, with AdditionSXTAH6, 7EM
SXTBSign extend ByteSXTB6
SXTHSign extend HalfwordSXTH6
SXTB16Sign extend two BytesSXTB166, 7EM
SYSExecute system coprocessor instructionSYS7A, 7R
TBB, TBHTable Branch Byte, HalfwordTBB and TBHT2
TEQTest EquivalenceTEQx6M
TSTTestTSTAll
UADD8, UADD16, UASXParallel Unsigned ArithmeticParallel add and subtract6, 7EM
UBFXUnsigned Bit Field eXtractUBFXT2
UDIVUnsigned divideUDIV7M, 7R
UHADD8, UHADD16, UHASX, UHSUB8, UHSUB16, UHSAXParallel Unsigned Halving ArithmeticParallel add and subtract6, 7EM
UMAALUnsigned Multiply Accumulate Accumulate LongUMAAL6, 7EM
 (64 <= 32 + 32 + 32 x 32)  
UMLALUnsigned Multiply AccumulateUMLALx6M
 (64 <= 32 x 32 + 64), (64 <= 32 x 32)  
UMULLUnsigned MultiplyUMULLx6M
 (64 <= 32 x 32 + 64), (64 <= 32 x 32)  
UQADD8, UQADD16, UQASX, UQSUB8, UQSUB16, UQSAXParallel Unsigned Saturating ArithmeticParallel add and subtract6, 7EM
USAD8Unsigned Sum of Absolute DifferencesUSAD86, 7EM
USADA8Accumulate Unsigned Sum of Absolute DifferencesUSADA86, 7EM
USATUnsigned SaturateUSAT6, x6M
USAT16Unsigned Saturate, parallel halfwordsUSAT166, 7EM
USUB8, USUB16, USAXParallel unsigned arithmeticParallel add and subtract6, 7EM
UXTABZero extend Byte with AdditionUXTAB6, 7EM
UXTAB16Zero extend two bytes with AdditionUXTAB166, 7EM
UXTAHZero extend Halfword with AdditionUXTAH6, 7EM
UXTBZero extend ByteUXTB6
UXTHZero extend HalfwordUXTH6
UXTB16Zero extend two bytesUXTB166, 7EM
V*See NEON and VFP Programming  
WFEWait For EventWFET2, 6M
WFIWait For InterruptWFIT2, 6M
YIELDYieldYIELDT2, 6M

[a] Entries in the Architecture column indicate that the instructions are available as follows:

All

All versions of the ARM architecture.

5

The ARMv5T*, ARMv6*, and ARMv7 architectures.

5E

The ARMv5TE, ARMv6*, and ARMv7 architectures.

6

The ARMv6* and ARMv7 architectures.

6M

The ARMv6-M and ARMv7 architectures.

x6M

Not available in the ARMv6-M architecture.

7

The ARMv7 architectures.

7M

The ARMv7-M architecture, including ARMv7E-M implementations.

x7M

Not available in the ARMv6-M or ARMv7-M architecture, or any ARMv7E-M implementation.

7EM

ARMv7E-M implementations but not in the ARMv7-M or ARMv6-M architecture.

7R

The ARMv7-R architecture.

7MP

The ARMv7 architectures that implement the Multiprocessing Extensions.

7VE

The ARMv7 architectures that implement the Virtualization Extensions.

J

The ARMv5TEJ, ARMv6*, and ARMv7 architectures.

K

The ARMv6K, and ARMv7 architectures.

T

The ARMv4T, ARMv5T*, ARMv6*, and ARMv7 architectures.

T2

The ARMv6T2 and above architectures.

XScale

XScale versions of the ARM architecture.

Z

If Security Extensions are implemented.