This option instructs the compiler to split
into two or more
--split_ldm is selected, the maximum
number of register transfers for an
is limited to:
five, for all
LDMs that do not load the PC
LDMs that load the PC.
Where register transfers beyond these limits are required,
STM instructions are used.
STMinstructions are split by default when
--split_ldmis used. However, the compiler might subsequently recombine the separate instructions into an
STMinstructions are split when
Some target hardware does not benefit from code built with
--split_ldm. For example:
It has no significant benefit for cached systems, or for processors with a write buffer.
It has no benefit for systems with non zero-wait-state memory, or for systems with slow peripheral devices. Interrupt latency in such systems is determined by the number of cycles required for the slowest memory or peripheral access. Typically, this is much greater than the latency introduced by multiple register transfers.