You copied the Doc URL to your clipboard.


This option instructs the compiler to split LDM and STM instructions into two or more LDM or STM instructions.

When --split_ldm is selected, the maximum number of register transfers for an LDM or STM instruction is limited to:

  • five, for all STMs

  • five, for LDMs that do not load the PC

  • four, for LDMs that load the PC.

Where register transfers beyond these limits are required, multiple LDM or STM instructions are used.


The --split_ldm option can be used to reduce interrupt latency on ARM systems that:

  • do not have a cache or a write buffer, for example, a cacheless ARM7TDMI

  • use zero-wait-state, 32-bit memory.


Using --split_ldm increases code size and decreases performance slightly.


  • Inline assembler LDM and STM instructions are split by default when --split_ldm is used. However, the compiler might subsequently recombine the separate instructions into an LDM or STM.

  • Only LDM and STM instructions are split when --split_ldm is used.

  • Some target hardware does not benefit from code built with --split_ldm. For example:

    • It has no significant benefit for cached systems, or for processors with a write buffer.

    • It has no benefit for systems with non zero-wait-state memory, or for systems with slow peripheral devices. Interrupt latency in such systems is determined by the number of cycles required for the slowest memory or peripheral access. Typically, this is much greater than the latency introduced by multiple register transfers.