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ARMv6 SIMD intrinsics

The ARM Architecture v6 Instruction Set Architecture adds many Single Instruction Multiple Data (SIMD) instructions to ARMv6 for the efficient software implementation of high-performance media applications.

The ARM compiler supports intrinsics that map to the ARMv6 SIMD instructions. These intrinsics are available when compiling your code for an ARMv6 architecture or processor. If the chosen architecture does not support the ARMv6 SIMD instructions, compilation generates a warning and subsequent linkage fails with an undefined symbol reference.


Each ARMv6 SIMD intrinsic is guaranteed to be compiled into a single, inline, machine instruction for an ARM v6 architecture or processor. However, the compiler might use optimized forms of underlying instructions when it detects opportunities to do so.

The ARMv6 SIMD instructions can set the GE[3:0] bits in the Application Program Status Register (APSR). Some SIMD instructions update these flags to indicate the greater than or equal to status of each 8 or 16-bit slice of an SIMD operation.

The ARM compiler treats the GE[3:0] bits as a global variable. To access these bits from within your C or C++ program, either:

  • access bits 16-19 of the APSR through a named register variable

  • use the __sel intrinsic to control a SEL instruction.

See also