Table A.1 shows the Cortex-M0 implementation options:
|Option||Description, and affected documentation|
|Number of interrupts|
The implementer decides how many interrupts the Cortex-M0 implementation supports, in the range 1-32. This affects the range of IRQ values in Table 2.5.
|Inclusion of the WIC|
The implementer decides whether to include the Wakeup interrupt Controller (WIC), see The optional Wakeup Interrupt Controller.
|Sleep mode power-saving|
The implementer decides what sleep modes to implement, and the power-saving measures associated with any implemented mode, see Power management.
Some features of the memory system are implementation-specific. This means that Memory model cannot completely describe the memory map for a specific Cortex-M0 implementation.
The SysTick timer and its SYST_CALIB register are implementation-defined. This can affect: