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A.1. Cortex-M0 implementation options

Table A.1 shows the Cortex-M0 implementation options:

Table A.1. Effects of the Cortex-M0 implementation options
OptionDescription, and affected documentation
Number of interrupts

The implementer decides how many interrupts the Cortex-M0 implementation supports, in the range 1-32. This affects the range of IRQ values in Table 2.5.

Inclusion of the WIC

The implementer decides whether to include the Wakeup interrupt Controller (WIC), see The optional Wakeup Interrupt Controller.

Sleep mode power-saving

The implementer decides what sleep modes to implement, and the power-saving measures associated with any implemented mode, see Power management.

Endianness

The implementer decides whether the memory system is little-endian or big-endian, see Data types and Memory endianness.

Memory features

Some features of the memory system are implementation-specific. This means that Memory model cannot completely describe the memory map for a specific Cortex-M0 implementation.

SysTick timer

The SysTick timer and its SYST_CALIB register are implementation-defined. This can affect:


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