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Using adaptive clocking to synchronize the JTAG port

ARM architecture-based devices using only hard macrocells, for example ARM7TDMI® and ARM920T, use the standard five-wire JTAG interface (TCK, TMS, TDI, TDO, and nTRST). Some target systems, however, require that JTAG events are synchronized to a clock in the system. To ensure a valid JTAG CLK setting, these systems often support an extra signal (RTCK) at the JTAG port:

  • an Application-Specific Integrated Circuit (ASIC) with single rising-edge D-type design rules, such as one based on an ARM7TDMI-S™ processor

  • a system where scan chains external to the ARM macrocell must meet single rising-edge D-type design rules.

The adaptive clocking feature of DSTREAM addresses this requirement. When adaptive clocking is enabled, DSTREAM issues a TCK signal and waits for the RTCK signal to come back. DSTREAM does not progress to the next TCK until RTCK is received.


  • Adaptive clocking is automatically configured in ARM DS-5™ as required by the target.

  • If you use the adaptive clocking feature, transmission delays, gate delays, and synchronization requirements result in a lower maximum clock frequency than with non-adaptive clocking. Do not use adaptive clocking unless it is required by the hardware design.

  • If, when autoconfiguring a target, the DSTREAM unit receives pulses on RTCK in response to TCK it assumes that adaptive clocking is required, and enables adaptive clocking in the target configuration. If the hardware does not require adaptive clocking, the target is driven slower than it could be. You can disable adaptive clocking using controls on the JTAG settings dialog box.

  • If adaptive clocking is used, DSTREAM cannot detect the clock speed, and therefore cannot scale its internal timeouts. If the target clock frequency is very slow, a JTAG timeout might occur. This leaves the JTAG in an unknown state, and DSTREAM cannot operate correctly without reconnecting to the processor. JTAG timeouts are enabled by default. You can disable JTAG timeouts by deselecting the option JTAG Timeouts Enabled in the installed RVConfig utility provided with the DSTREAM unit.

You can use adaptive clocking as an interface to targets with slow or widely varying clock frequency, such as battery-powered equipment that varies its clock speed according to processing demand. In this system, TCK might be hundreds of times faster than the system clock, and the debugger loses synchronization with the target system. Adaptive clocking ensures that the JTAG port speed automatically adapts to slow system speed.

The following figure shows a circuit for a basic JTAG port synchronizer.

Figure 1. Basic JTAG port synchronizer

Figure 1. Basic JTAG port synchronizer

The following figure shows a partial timing diagram for the basic JTAG synchronizer. The delay can be reduced by clocking the flip-flops from opposite edges of the system clock, because the second flip-flop only provides better immunity to metastability problems. Even a single flip-flop synchronizer never completely misses TCK events, because RTCK is part of a feedback loop controlling TCK.

Figure 2. Timing diagram for the Basic JTAG synchronizer

Figure 2. Timing diagram for the Basic JTAG

It is common for an ASIC design flow and its design rules to impose a restriction that all flip-flops in a design are clocked by one edge of a single clock. To interface this to a JTAG port that is completely asynchronous to the system, it is necessary to convert the JTAG TCK events into clock enables for this single clock, and to ensure that the JTAG port cannot overrun this synchronization delay.

The following figure shows one possible implementation of this circuit.

Figure 3. JTAG port synchronizer for single rising-edge D-type ASIC design rules

Figure 3. JTAG port synchronizer for single
rising-edge D-type ASIC design rules

The following figure shows a corresponding partial timing diagram, and how TCKFallingEn and TCKRisingEn are each active for exactly one period of CLK. It also shows how these enable signals gate the RTCK and TDO signals so that they only change state at the edges of TCK.

Figure 4. Timing diagram for the D-type JTAG synchronizer

Figure 4. Timing diagram for the D-type JTAG

See also