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ARM JTAG 14

The ARM JTAG 14 connector can be used in either standard JTAG (IEEE 1149.1) mode or Serial Wire Debug (SWD) mode.

The following figure shows the TI JTAG 14 connector pinout:

Figure 16. ARM JTAG 14 connector pinout

Figure 16. ARM JTAG 14 connector pinout

The following table shows the ARM JTAG 14 pinout as used on the target board:

Table 10. ARM JTAG 14 interface pinout table
PinSignal nameI/O diagramVoltage domain
1NCNANA
2GNDHNA
3nTRSTDA
4GNDHNA
5TDIBA
6GNDHNA
7TMS/SWDIOBA
8GNDHNA
9TCK/SWCLKBA
10GNDHNA
11TDO/SWOAA
12nSRSTEA
13VTREFFA
14GNDHNA

The following table describes the signals on the ARM JTAG 14 interfaces:

Table 11. ARM JTAG 14 signals
SignalI/ODescription
TDIOutputThe Test Data In pin provides serial data to the target during debugging. TDI can be pulled HIGH on the target.
TDOInputThe Test Data Out pin receives serial data from the target during debugging. You are advised to series terminate TDO close to the target processor. TDO is typically pulled HIGH on the target.
TMSOutputThe Test Mode Select pin is used to set the state of the Test Access Port (TAP) controller on the target. TMS can be pulled HIGH on the target to keep the TAP controller inactive when not in use.
TCKOutputThe Test Clock pin is used to clock data into the TDI and TMS inputs of the target. TCK is typically pulled HIGH on the target.
nTRSTOutputThe Test Reset pin can be used to reset the TAP controller of the processor to allow debugging to take place. nTRST is typically pulled HIGH on the target and pulled strong-LOW by DSTREAM to initiate a reset. The polarity and strength of nTRST is configurable.
nSRSTInput/OutputThe System Reset pin is used to fully reset the target. This signal can be initiated by DSTREAM or by the target board (which is then detected by DSTREAM). nSRST is typically pulled HIGH on the target and pulled strong-LOW to initiate a reset. The polarity and strength of nSRST is configurable.
SWDIO (SWD mode)Input/OutputThe Serial Wire Data I/O pin sends and receives serial data to and from the target during debugging. You are advised to series terminate SWDIO close to the target processor.
SWCLK(SWD mode)OutputThe Serial Wire Clock pin clocks data into and out of the target during debugging.
SWO (SWD mode)InputThe Serial Wire Output pin can be used to provide trace data to DSTREAM. You are advised to series terminate SWO close to the target processor.
VTREFInputThe Voltage Target Reference pin supplies DSTREAM with the debug rail voltage of the target to match its I/O logic levels. VTREF can be tied HIGH on the target. If VTREF is pulled HIGH by a resistor, its value must be no greater than 100Ω.
GND-Ground.

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