The Mictor 38 connector is intended for high-speed trace capture of up to 16 bits of trace data and status/sync signals. It can also be used to connect to the debug signals of the target.
Note
This connector supports only one voltage domain. If the trace and debug signals of the target system use different logic levels, the target must be designed to use a separate debug connector. If a separate connector is used for the debug signals, the unused debug pins of the Mictor 38 connector can be left open circuit.
The central earthing strip on the connector provides signal ground. This strip has five through-hole pins, and to achieve reliable trace operation these pins must be soldered directly to the ground plane of the target board.
The following figure shows the Mictor 38 connector pinout:
Due to the construction of the Mictor cable, the signals on the probe itself are column-reversed (1-37, 37-1, 2-38, 38-2, and so on). Only take this into account if testing signals at the probe.
The following table shows the Mictor 38 pinout as used on the target board:
| Pin | ETMv3/TPIU | ETMv2 | ETMv1 | I/O diagram | Voltage domain |
|---|---|---|---|---|---|
| 1 | NC | NC | NC | NA | NA |
| 2 | NC | NC | NC | NA | NA |
| 3 | NC | NC | NC | NA | NA |
| 4 | NC | NC | NC | NA | NA |
| 5 | GND | GND | GND | H | NA |
| 6 | TRACECLK | TRACECLK | TRACECLK | A | B |
| 7 | DBGRQ | DBGRQ | DBGRQ | B | B |
| 8 | DBGACK | DBGACK | DBGACK | A | B |
| 9 | nSRST | nSRST | nSRST | E | B |
| 10 | EXTTRIG | EXTTRIG | EXTTRIG | B | B |
| 11 | TDO | TDO | TDO | A | B |
| 12 | VTREF | VTREF | VTREF | F | B |
| 13 | RTCK | RTCK | RTCK | B | B |
| 14 | VSUPPLY | VSUPPLY | VSUPPLY | Reserved | NA |
| 15 | TCK | TCK | TCK | B | B |
| 16 | TRACEDATA[7] | TRACEPKT[7] | TRACEPKT[7] | A | B |
| 17 | TMS | TMS | TMS | B | B |
| 18 | TRACEDATA[6] | TRACEPKT[6] | TRACEPKT[6] | A | B |
| 19 | TDI | TDI | TDI | B | B |
| 20 | TRACEDATA[5] | TRACEPKT[5] | TRACEPKT[5] | A | B |
| 21 | nTRST | nTRST | nTRST | D | B |
| 22 | TRACEDATA[4] | TRACEPKT[4] | TRACEPKT[4] | A | B |
| 23 | TRACEDATA[15] | TRACEPKT[15] | TRACEPKT[15] | A | B |
| 24 | TRACEDATA[3] | TRACEPKT[3] | TRACEPKT[3] | A | B |
| 25 | TRACEDATA[14] | TRACEPKT[14] | TRACEPKT[14] | A | B |
| 26 | TRACEDATA[2] | TRACEPKT[2] | TRACEPKT[2] | A | B |
| 27 | TRACEDATA[13] | TRACEPKT[13] | TRACEPKT[13] | A | B |
| 28 | TRACEDATA[1] | TRACEPKT[1] | TRACEPKT[1] | A | B |
| 29 | TRACEDATA[12] | TRACEPKT[12] | TRACEPKT[12] | A | B |
| 30 | Logic 0 | TRACEPKT[0] | TRACEPKT[0] | A | B |
| 31 | TRACEDATA[11] | TRACEPKT[11] | TRACEPKT[11] | A | B |
| 32 | Logic 0 | PIPESTAT[3] | TRACESYNC | A | B |
| 33 | TRACEDATA[10] | TRACEPKT[10] | A | B | |
| 34 | Logic 1 | PIPESTAT[2] | PIPESTAT[2] | A | B |
| 35 | TRACEDATA[9] | TRACEPKT[9] | TRACEPKT[9] | A | B |
| 36 | TRACECTL | PIPESTAT[1] | PIPESTAT[1] | A | B |
| 37 | TRACEDATA[8] | TRACEPKT[8] | TRACEPKT[8] | A | B |
| 38 | TRACEDATA[0] | PIPESTAT[0] | PIPESTAT[0] | A | B |
The following table describes the signals on the Mictor 38 interfaces:
| Signal | I/O | Description |
|---|---|---|
| TRACEPKT, TRACEDATA, PIPESTAT, TRACESYNC, TRACECTL | Input | These pins provide DSTREAM with ETM/TPIU trace data in the various formats shown above. You are advised to series terminate these signals close to the target processor. |
| TRACECLK | Input | The Trace Clock pin provides DSTREAM with the clock signal necessary to sample all of the trace data signals above. You are advised to series terminate TRACECLK close to the target processor. |
| TDI | Output | The Test Data In pin provides serial data to the target during debugging. TDI can be pulled HIGH on the target. |
| TDO | Input | The Test Data Out pin receives serial data from the target during debugging. You are advised to series terminate TDO close to the target processor. TDO is typically pulled HIGH on the target. |
| TMS | Output | The Test Mode Select pin is used to set the state of the Test Access Port (TAP) controller on the target. TMS can be pulled HIGH on the target to keep the TAP controller inactive when not in use. |
| TCK | Output | The Test Clock pin is used to clock data into the TDI and TMS inputs of the target. TCK is typically pulled HIGH on the target. |
| RTCK | Input | The Return Test Clock pin is used to echo the test clock signal back to DSTREAM for use with adaptive mode clocking. If RTCK is generated by the target processor, you are advised to series terminate it. RTCK can be pulled HIGH or LOW on the target when not in use. |
| nTRST | Output | The Test Reset pin can be used to reset the TAP controller of the processor to allow debugging to take place. nTRST is typically pulled HIGH on the target and pulled strong-LOW by DSTREAM to initiate a reset. The polarity and strength of nTRST is configurable. |
| nSRST | Input/Output | The System Reset pin is used to fully reset the target. This signal can be initiated by DSTREAM or by the target board (which is then detected by DSTREAM). nSRST is typically pulled HIGH on the target and pulled strong-LOW to initiate a reset. The polarity and strength of nSRST is configurable. |
| DBGRQ | Output | The Debug Request pin can be used to stop the target processor and put it into debug state. DBGRQ is rarely used by current systems and is usually pulled LOW on the target. |
| DBGACK | Input | The Debug Acknowledge pin can be used to notify DSTREAM that a debug request has been received and the target processor is now in debug state. DBGACK is rarely used by current systems and is usually pulled LOW on the target. |
| VTREF | Input | The Voltage Target Reference pin supplies DSTREAM with the debug rail voltage of the target to match its I/O logic levels. VTREF can be tied HIGH on the target. If VTREF is pulled HIGH by a resistor, its value must be no greater than 100Ω. |
| VSUPPLY | - | The Voltage Supply pin is not used by DSTREAM and must be left unconnected. |
| GND | - | Ground. |