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SWD timing requirements

The interface uses only two lines, but for clarity the diagrams shown in the following figure separate the SWDIO line to show when it is driven by either the DSTREAM probe or target:

Figure 11. SWD timing diagrams

Figure 11. SWD timing diagrams

The probe writes data to SWDIO on the falling edge of SWDCLK. The probe reads data from SWDIO on the rising edge of SWDCLK. The target writes data to SWDIO on the rising edge of SWDCLK. The target reads data from SWDIO on the rising edge of SWDCLK.

The following table shows the timing requirements for the Serial Wire Debug (SWD):

Table 2. SWD timing requirements
ParameterMinMaxDescription
Thigh10ns500μsSWDCLK HIGH period
Tlow10ns500μsSWDCLK LOW period
Tos-5ns5nsSWDIO Output skew to falling edge SWDCLK
Tis4ns-Input Setup time required between SWDIO and rising edge SWDCLK
Tih1ns-Input Hold time required between SWDIO and rising edge SWDCLK

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