All ARM processors have a main processor reset that might be called nRESET, BnRES, or HRESET. This is asserted by one or more of these conditions:
manual push button
remote reset from the debugger (using )
watchdog circuit (if appropriate to the application).
Any ARM processor including the JTAG interface has a second reset input called nTRST (TAP Reset). This resets the EmbeddedICE logic, the Test Access Port (TAP) controller, and the boundary scan cells. It is activated by remote JTAG reset (from ).
It is strongly recommended that both signals are separately available on the JTAG connector. If the nRESET and nTRST signals are linked together, resetting the system also resets the TAP controller. This means that:
it is not possible to debug a system from reset, because any breakpoints previously set are lost
you might have to start the debug session from the beginning, because DSTREAM might not recover when the TAP controller state is changed.