The CoreSight 10 connector can be used in either standard JTAG (IEEE 1149.1) mode or Serial Wire Debug (SWD) mode.
The following figure shows the CoreSight 10 connector pinout:
A polarizing key is fitted only at the target end of the cable.
The following table shows the CoreSight 10 pinout as used on the target board:
|Pin||Signal name||I/O diagram||Voltage domain|
The following table describes the signals on the CoreSight 10 interfaces:
|TDI||Output||The Test Data In pin provides serial data to the target during debugging. TDI can be pulled HIGH on the target.|
|TDO||Input||The Test Data Out pin receives serial data from the target during debugging. You are advised to series terminate TDO close to the target processor. TDO is typically pulled HIGH on the target.|
|TMS||Output||The Test Mode Select pin is used to set the state of the Test Access Port (TAP) controller on the target. TMS can be pulled HIGH on the target to keep the TAP controller inactive when not in use.|
|TCK||Output||The Test Clock pin is used to clock data into the TDI and TMS inputs of the target. TCK is typically pulled HIGH on the target.|
|nSRST||Input/Output||The System Reset pin is used to fully reset the target. This signal can be initiated by DSTREAM or by the target board (which is then detected by DSTREAM). nSRST is typically pulled HIGH on the target and pulled strong-LOW to initiate a reset. The polarity and strength of nSRST is configurable.|
|SWDIO (SWD mode)||Input/Output||The Serial Wire Data I/O pin sends and receives serial data to and from the target during debugging. You are advised to series terminate SWDIO close to the target processor.|
|SWCLK(SWD mode)||Output||The Serial Wire Clock pin clocks data into and out of the target during debugging.|
|SWO (SWD mode)||Input||The Serial Wire Output pin can be used to provide trace data to DSTREAM. You are advised to series terminate SWO close to the target processor.|
|VTREF||Input||The Voltage Target Reference pin supplies DSTREAM with the debug rail voltage of the target to match its I/O logic levels. VTREF can be tied HIGH on the target. If VTREF is pulled HIGH by a resistor, its value must be no greater than 100Ω.|
|KEY||-||This pin must not be present on the target connector.|