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MIPI 34

The MIPI 34 connector can be used in either standard JTAG (IEEE 1149.1) mode or Serial Wire Debug (SWD) mode. It can also capture up to 4-bits of parallel trace in Trace Port Interface Unit (TPIU) continuous mode.

This connector supports separate voltage domains for the debug and trace signals. It is therefore necessary to supply the appropriate voltages to both of the VTREF pins.

The following figure shows the MIPI 34 connector pinout:

Figure 19. MIPI 34 connector pinout

Figure 19. MIPI 34 connector pinout

Note

A polarizing key is fitted only at the target end of the cable.

The following table shows the MIPI 34 pinout as used on the target board:

Table 16. MIPI 34 interface pinout table
PinSignal nameI/O diagramVoltage domain
1VTREFGA
2TMS/SWDIOBA
3GNDHNA
4TCK/SWCLKBA
5GNDHNA
6TDO/SWOAA
7KEY (NC)NANA
8TDIBA
9GNDHNA
10nSRSTEA
11NCINA
12RTCKAA
13NCINA
14TRST_PDDA
15GNDHNA
16nTRSTDA
17GNDHNA
18DBGRQBA
19GNDHNA
20DBGACKAA
21GNDHNA
22TRACECLKAB
23GNDHNA
24TRACED0AB
25GNDHNA
26TRACED1AB
27GNDHNA
28TRACED2AB
29GNDHNA
30TRACED3AB
31GNDHNA
32TRACEEXTCB
33GNDHNA
34VTREFFB

The following table describes the signals on the MIPI 34 interfaces:

Table 17. MIPI 34 signals
SignalI/ODescription
TDIOutputThe Test Data In pin provides serial data to the target during debugging. TDI can be pulled HIGH on the target.
TDOInputThe Test Data Out pin receives serial data from the target during debugging. You are advised to series terminate TDO close to the target processor. TDO is typically pulled HIGH on the target.
TMSOutputThe Test Mode Select pin is used to set the state of the Test Access Port (TAP) controller on the target. TMS can be pulled HIGH on the target to keep the TAP controller inactive when not in use.
TCKOutputThe Test Clock pin is used to clock data into the TDI and TMS inputs of the target. TCK is typically pulled HIGH on the target.
RTCKInputThe Return Test Clock pin is used to echo the test clock signal back to DSTREAM for use with adaptive mode clocking. If RTCK is generated by the target processor, you are advised to series terminate it. RTCK can be pulled HIGH or LOW on the target when not in use.
nTRSTOutputThe Test Reset pin can be used to reset the TAP controller of the processor to allow debugging to take place. nTRST is typically pulled HIGH on the target and pulled strong-LOW by DSTREAM to initiate a reset. The polarity and strength of nTRST is configurable.
TRST_PDOutputThe Test Reset (Pull-Down) pin can be used to reset the TAP controller of the processor to allow debugging to take place. TRST_PD is typically pulled LOW on the target (reset state) and pulled strong-HIGH by DSTREAM to enable debugging. The polarity and strength of TRST_PD is configurable.
nSRSTInput/OutputThe System Reset pin is used to fully reset the target. This signal can be initiated by DSTREAM or by the target board (which is then detected by DSTREAM). nSRST is typically pulled HIGH on the target and pulled strong-LOW to initiate a reset. The polarity and strength of nSRST is configurable.
DBGRQOutputThe Debug Request pin can be used to stop the target processor and put it into debug state. DBGRQ is rarely used by current systems and is usually pulled LOW on the target.
DBGACKInputThe Debug Acknowledge pin can be used to notify DSTREAM that a debug request has been received and the target processor is now in debug state. DBGACK is rarely used by current systems and is usually pulled LOW on the target.
SWDIO (SWD mode)Input/OutputThe Serial Wire Data I/O pin sends and receives serial data to and from the target during debugging. You are advised to series terminate SWDIO close to the target processor.
SWCLK(SWD mode)OutputThe Serial Wire Clock pin clocks data into and out of the target during debugging.
SWO (SWD mode)InputThe Serial Wire Output pin can be used to provide trace data to DSTREAM. You are advised to series terminate SWO close to the target processor.
TraceD[0-3]InputThe Trace Data [0-3] pins provide DSTREAM with Trace Port Interface Unit (TPIU) continuous mode trace data from the target. You are advised to series terminate these signals close to the target processor.
TRACECLKInputThe Trace Clock pin provides DSTREAM with the clock signal necessary to sample the trace data signals. You are advised to series terminate TRACECLK close to the target processor.
TRACEEXTInputThe Trace Extension pin is a generic trace sideband pin. TRACEEXT is not currently supported by DSTREAM. TRACEEXT can be pulled high, low, or left unconnected on the target.
VTREFInputThe Voltage Target Reference pin supplies DSTREAM with the debug rail voltage of the target to match its I/O logic levels. VTREF can be tied HIGH on the target. If VTREF is pulled HIGH by a resistor, its value must be no greater than 100Ω.
GND-Ground.
KEY-This pin must not be present on the target connector.

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