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Mictor 38 interface signals

The table describes the signals on the Mictor 38 interface.

Table 2-5 Mictor 38 signals

Signal I/O Description
TRACEPKT, TRACEDATA, PIPESTAT, TRACESYNC, TRACECTL Input These pins provide DSTREAM with ETM/TPIU trace data in the various formats shown above. You are advised to series terminate these signals close to the target processor.
TRACECLK Input The Trace Clock pin provides DSTREAM with the clock signal necessary to sample all of the trace data signals above. You are advised to series terminate TRACECLK close to the target processor.
TDI Output The Test Data In pin provides serial data to the target during debugging. TDI can be pulled HIGH on the target.
TDO Input The Test Data Out pin receives serial data from the target during debugging. You are advised to series terminate TDO close to the target processor. TDO is typically pulled HIGH on the target.
TMS Output The Test Mode Select pin sets the state of the Test Access Port (TAP) controller on the target. TMS can be pulled HIGH on the target to keep the TAP controller inactive when not in use.
TCK Output The Test Clock pin clocks data into the TDI and TMS inputs of the target. TCK is typically pulled HIGH on the target.
RTCK Input The Return Test Clock pin echos the test clock signal back to DSTREAM for use with adaptive mode clocking. If RTCK is generated by the target processor, you are advised to series terminate it. RTCK can be pulled HIGH or LOW on the target when not in use.
nTRST Output The Test Reset pin resets the TAP controller of the processor to allow debugging to take place. nTRST is typically pulled HIGH on the target and pulled strong-LOW by DSTREAM to initiate a reset. The polarity and strength of nTRST is configurable.
nSRST Input/Output The System Reset pin fully resets the target. This signal can be initiated by DSTREAM or by the target board (which is then detected by DSTREAM). nSRST is typically pulled HIGH on the target and pulled strong-LOW to initiate a reset. The polarity and strength of nSRST is configurable.
DBGRQ Output The Debug Request pin stops the target processor and puts it into debug state. DBGRQ is rarely used by current systems and is usually pulled LOW on the target.
DBGACK Input The Debug Acknowledge pin notifies DSTREAM that a debug request has been received and the target processor is now in debug state. DBGACK is rarely used by current systems and is usually pulled LOW on the target.
VTREF Input The Voltage Target Reference pin supplies DSTREAM with the debug rail voltage of the target to match its I/O logic levels. VTREF can be tied HIGH on the target. If VTREF is pulled HIGH by a resistor, its value must be no greater than 100Ω.
VSUPPLY - The Voltage Supply pin is not used by DSTREAM and must be left unconnected.
GND - Ground.
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