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A.2. HDRX HSB multiplexing scheme

A bus multiplexing scheme is necessary to reduce the number of pins required on the HDRX header for the 64-bit AXI master and slave on the HSBM and HSBS buses. The LogicTile Express daughterboard must implement a similar multiplexing scheme to be compatible with the CoreTile Express signals.

OSCCLK1, on the CoreTile Express A5x2 daughterboard, generates the AXI master bus clock. This clocks the test chip master multiplex and demultiplex logic. This logic is positive- and negative-edge triggered to avoid the requirement for a PLL or double-rate clock in the test chip. Double-edge clocking also enables operation at low speed for use with emulation systems.

The AXI slave bus uses a similar method, but the clock source is on site 2. See Figure A.2.


All signals on the HSB (M) and HSB (S) buses are 1.8V.

Figure A.2 shows a simplified block diagram of the multiplexing scheme for the two AXI buses.

Figure A.2. HSB multiplexing

Figure A.2. HSB multiplexing

Application note AN243, Example LogicTile Express 3MG design for a CoreTile Express A5x2, provided by ARM, implements an example AMBA system using a LogicTile Express 3MG daughterboard to interconnect with the CoreTile Express A5x2 daughterboard. See the documentation supplied on the accompanying media and the Application Notes listing for more information at

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