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3.3.7. Test chip SCC registers

The SCC register interface enables configuration of power-up in addition to reading and writing of system parameters. The SCC registers use a dedicated interface to the Daughterboard Configuration Controller that communicates with the MCC over an SPI interface.

The MCC on the motherboard reads the config.txt and board.txt configuration files and uses the Daughterboard Configuration Controller to configure the motherboard and attached daughterboards. The Daughterboard Configuration Controller loads some of the registers in the test chip SCC.

Run-time read and write operations are performed through the SYS_CFG registers, or directly through the APB interface at base address 0x2A100000.

Note

ARM recommends that, where possible, you perform all system configuration by loading configuration files into the flash memory on the motherboard rather than writing directly to the test chip controller. The settings in the board.txt file are applied to the daughterboard before reset is released.

Interface to test chip SCC

You can read from and write to the Cortex-A5 MPCore test chip SCC registers:

  • The interface supports word writes to the configuration controller registers.

  • Writes to read-only registers are ignored.

  • Writes to unused words fail. ARM recommends that you use a read-modify-write sequence to update the configuration controller registers.

  • Read accesses to the peripheral support reading back 32 bits of the register at a time.

  • Reads from unused words in the register return zero.

  • The base address of the SCC registers is 0x2A100000.

Table 3.2 shows the configuration registers and corresponding offsets from the base memory address. The offsets are also their board.txt entries.

Table 3.2. Test chip SCC register summary

Offset

Name

Type

Reset

Description

SCC: 0x000CFGRW0RW0x400F0000 Test chip SCC Register 0.
SCC: 0x004CFGRW1RW0x40882110Test chip SCC Register 1.
SCC: 0x010CFGRW2RW0x14FC00FC Test chip SCC Register 2.
SCC: 0x014CFGRW3RW0x01CFC18FCTest chip SCC Register 3.
SCC: 0x018CFGRW4RW0x10FC0CFCTest chip SCC Register 4.
SCC: 0x01CCFGRW5RW0x08FC04FCTest chip SCC Register 5.
SCC: 0x190CFGRW6RO0x07220477Test chip SCC Register 6.
SCC: 0x194CFGRW7RO-Test chip SCC Register 7.
SCC: 0x008-0xFF0---Reserved. Do not write to or read from these registers.
SCC: 0xFF4APBCLEARWO-Test chip SCC Register APBCLEAR.
SCC: 0xFF8DEVICEIDRO0x00050387Test chip SCC Register DEVICEID.
SCC: 0xFFCCPUIDRO0x410FC051Test chip SCC Register CPUID.

Test chip SCC Register 0

The CFGRW0 Register characteristics are:

Purpose

Enables you to read and write test chip configuration settings.

Usage constraints

CFGRW0[31:30] = 00 or 11 are reserved and must not be used. These bits are valid only if CFGRW0[0] is b0.

Configurations

Available in all CoreTile Express A5x2 daughterboard configurations.

Attributes

Figure 3.3 shows the bit assignments.

Figure 3.3. Test chip CFGRW0 Register bit assignments

Figure 3.3. Test chip CFGRW0 Register bit assignments

Table 3.3 shows the bit assignments.

Table 3.3. Test chip CFGRW0 Register bit assignments
BitsNameFunction
[31:30]SMC remap

These map to the SMC_REMAP[1:0] bus:

b00

Reserved.

b01

CS0.

b10

CS4.

b11

Reserved.

These bits are valid only if SMC is mapped to 0x0, that is CFGRW0[0] = b0.

[29]CFGDISABLE

GIC configuration disable.

[28:27]-

Reserved. Do not modify.

[26:25]CP15_DISABLE_CPU[1:0]

Maps to the CP15_DISABLE_CPU[1:0] bus.

[24]CFGBIGENDIAN_L2_Cache

Maps to the CFGBIGENDIAN_L2_Cache signal.

[23:22]-

Reserved. Do not modify.

[21:20]CFGEND[1:0]

Maps to the CFGEND[1:0] bus. Configures CPUs as bigend.

[19]SPNIDEN

Maps to the SPNIDEN secure non-invasive debug signal for both CPUs.

[18]SPIDEN

Maps to the SPIDEN secure invasive debug signal for both CPUs.

[17]NIDEN

Maps to the NIDEN non-invasive debug enable signal.

[16]DBGEN

Maps to the DBGEN invasive debug enable signal.

[15:14]-

Reserved. Do not modify.

[13:12]THUMBNIT_CORE[1:0]Thumbnit input for CPU[1:0]
[11:10]-

Reserved. Do not modify.

[9:8]VINITHI_CORE[1:0]Vinithi input for CPU[1:0].
[7:4]CLUSTERIDMaps to the CLUSTERID[3:0] bus.
[3:1]-Reserved. Do not modify.
[0]AXIBM_REMAP

NIC-301 AMBA AXI memory map:

b0

SMC mapped to 0x0.

b1

AXI Master interface mapped to 0x0.


Test chip SCC Register 1

The CFGRW1 Register characteristics are:

Purpose

Enables you to read and write test chip configuration settings.

Usage constraints

There are no usage constraints.

Configurations

Available in all CoreTile Express A5x2 daughterboard configurations.

Attributes

Figure 3.4 shows the bit assignments.

Figure 3.4. Test chip CFGRW1 Register bit assignments

Figure 3.4. Test chip CFGRW1 Register bit assignments

Table 3.4 shows the bit assignments.

Table 3.4. Test chip CFGRW1 register bit assignments
BitsNameFunction
[31]-

Reserved. Do not modify.

[30:29]ADDRTRANS_MXSIF

Translates External Slave Interface address by overriding bits [31:30] of AxADDR:

b00

0x0000_0000

b10

0x8000_0000

b11

0xC000_0000

For V2P-CA5s, 0xC000_0000 is aliased to 0x8000_000.

[28]ADDRTRANS_ENABLEEnables external slave interface address translation.
[27]-

Reserved. Do not modify.

[26]ADDRTRANS_ACP

Translates the ACP address by overriding bit 28 of AxADDR of the cluster ACP port.

b0

0xE000_0000

For V2 A5, 0xE000_0000 is aliased to 0xA000_0000.

b1

0xF000_0000

For V2P-CA5s, 0xF000_0000 is aliased to 0xB000_000.

[25:22]AWCACHE_ACPACP AWCACHE override, default cacheable but do not allocate.
[21:18]ARCACHE_ACPACP ARCACHE override, default cacheable but do not allocate.
[17:13]AWUSERS_ACPACP AWUSERS override, default shareable.
[12:8]ARUSERS_ACPACP ARUSERS override, default shareable.
[7]AXCACHE_OVERRIDE_ENABLEEnables override of caching attributes on the CPU coherency port.
[6]AXUSERS_OVERRIDE_ENABLEEnables override of share attributes on the CPU coherency port.
[5]-

Reserved. Do not modify.

[4]DQSCHOKE_DISABLE_CFG

Disable internal masking of DQS in between DDR2 reads.

[3:0]-

Reserved. Do not modify.


Test chip SCC Register 2

The CFGRW2 Register characteristics are:

Purpose

Enables you to read and write test chip configuration settings.

Usage constraints

There are no usage constraints.

Configurations

Available in all CoreTile Express A5x2 daughterboard configurations.

Attributes

Figure 3.5 shows the bit assignments.

Figure 3.5. Test chip CFGRW2 Register bit assignments

Figure 3.5. Test chip CFGRW2 Register bit assignments

Table 3.5 shows the bit assignments.

Table 3.5. Test chip CFGRW2 Register bit assignments
BitsNameFunction
[31:24]SMC_ADDR_MATCH0_1

SMC CS1 address match of top 8 bits

[23:16]SMC_ADDR_MASK0_1

SMC CS1 address mask of top 8 bits

[15:8]SMC_ADDR_MATCH0_0

SMC CS0 address match of top 8 bits

[7:0]SMC_ADDR_MASK0_0

SMC CS0 address mask of top 8 bits


Test chip SCC Register 3

The CFGRW3 Register characteristics are:

Purpose

Enables you to read and write test chip configuration settings.

Usage constraints

There are no usage constraints.

Configurations

Available in all CoreTile Express A5x2 daughterboard configurations.

Attributes

Figure 3.6 shows the bit assignments.

Figure 3.6. Test chip CFGRW3 Register bit assignments

Figure 3.6. Test chip CFGRW3 Register bit assignments

Table 3.6 shows the bit assignments.

Table 3.6. Test chip CFGRW3 Register bit assignments
BitsNameFunction
[31:24]SMC_ADDR_MATCH0_3

SMC CS3 address match of top 8 bits

[23:16]SMC_ADDR_MASK0_3

SMC CS3 address mask of top 8 bits

[15:8]SMC_ADDR_MATCH0_2

SMC CS2 address match of top 8 bits

[7:0]SMC_ADDR_MASK0_2

SMC CS2 address mask of top 8 bits


Test chip SCC Register 4

The CFGRW4 Register characteristics are:

Purpose

Enables you to read and write test chip configuration settings.

Usage constraints

There are no usage constraints.

Configurations

Available in all CoreTile Express A5x2 daughterboard configurations.

Attributes

Figure 3.7 shows the bit assignments.

Figure 3.7. Test chip CFGRW4 Register bit assignments

Figure 3.7. Test chip CFGRW4 Register bit assignments

Table 3.7 shows the bit assignments.

Table 3.7. Test chip CFGRW4 Register bit assignments
BitsNameFunction
[31:24]SMC_ADDR_MATCH1_1

SMC CS5 address match of top 8 bits

[23:16]SMC_ADDR_MASK1_1

SMC CS5 address mask of top 8 bits

[15:8]SMC_ADDR_MATCH1_0

SMC CS4 address match of top 8 bits

[7:0]SMC_ADDR_MASK1_0

SMC CS4 address mask of top 8 bits


Test chip SCC Register 5

The CFGRW5 Register characteristics are:

Purpose

Enables you to read and write test chip configuration settings.

Usage constraints

There are no usage constraints.

Configurations

Available in all CoreTile Express A5x2 daughterboard configurations.

Attributes

Figure 3.8 shows the bit assignments.

Figure 3.8. Test chip CFGRW5 Register bit assignments

Figure 3.8. Test chip CFGRW5 Register bit assignments

Table 3.8 shows the bit assignments.

Table 3.8. Test chip CFGRW5 Register bit assignments
BitsNameFunction
[31:24]SMC_ADDR_MATCH1_3

SMC CS7 address match of top 8 bits

[23:16]SMC_ADDR_MASK1_3

SMC CS7 address mask of top 8 bits

[15:8]SMC_ADDR_MATCH1_2

SMC CS6 address match of top 8 bits

[7:0]SMC_ADDR_MASK1_2

SMC CS6 address mask of top 8 bits


Test chip SCC Register 6

The CFGRW6 Register characteristics are:

Purpose

Enables you to read the DAP ROM default target ID.

Usage constraints

This register is read only.

Configurations

Available in all CoreTile Express A5x2 daughterboard configurations.

Attributes

Figure 3.9 shows the bit assignments.

Figure 3.9. Test chip CFGRW6 Register bit assignments

Figure 3.9. Test chip CFGRW6 Register bit assignments

Table 3.9 shows the bit assignments.

Table 3.9. Test chip CFGRW6 Register bit assignments
BitsNameFunction
[31:0]-

DAP ROM default target ID


Test chip SCC Register 7

The CFGRW7 Register characteristics are:

Purpose

Enables you to read the DAP ROM default instance ID.

Usage constraints

This register is read only.

Configurations

Available in all CoreTile Express A5x2 daughterboard configurations.

Attributes

Figure 3.10 shows the bit assignments.

Figure 3.10. Test chip CFGRW7 Register bit assignments

Figure 3.10. Test chip CFGRW7 Register bit assignments

Table 3.10 shows the bit assignments.

Table 3.10. Test chip CFGRW7 Register bit assignments
BitsNameFunction
[31:0]-

DAP ROM default instance ID


Test chip SCC Register APBCLEAR

The APBCLEAR Register characteristics are:

Purpose

Writing 0xA50FF05A to this register reverts the serial control registers to the values loaded through the serial configuration values.

Usage constraints

This register is write-only.

Configurations

Available in all CoreTile Express A5x2 daughterboard configurations.

Attributes

Figure 3.11 shows the bit assignments.

Figure 3.11. Test chip APBCLEAR Register bit assignments

Figure 3.11. Test chip APBCLEAR Register bit assignments

Table 3.11 shows the bit assignments.

Table 3.11. Test chip APBCLEAR Register bit assignments
BitsNameFunction
[31:0]-

Writing 0xA50FF05A to this register reverts the serial control registers to the values loaded through the serial configuration values.


Test chip SCC Register DEVICEID

The DEVICEID Register characteristics are:

Purpose

Enables you to read the Cortex-A5 MPCore test chip specific device ID.

Usage constraints

This register is read-only.

Configurations

Available in all CoreTile Express A5x2 daughterboard configurations.

Attributes

Figure 3.12 shows the bit assignments.

Figure 3.12. Test chip DEVICEID Register bit assignments

Figure 3.12. Test chip DEVICEID Register bit assignments

Table 3.12 shows the bit assignments.

Table 3.12. Test chip DEVICEID Register bit assignments
BitsNameFunction
[31:0]-

Cortex-A5 test chip device ID


Test chip SCC Register CPUID

The CPUID Register characteristics are:

Purpose

Enables you to read the Cortex-A5 MPCore test chip CPU ID.

Usage constraints

This register is read-only.

Configurations

Available in all CoreTile Express A5x2 daughterboard configurations.

Attributes

Figure 3.13 shows the bit assignments.

Figure 3.13. Test chip CPUID Register bit assignments

Figure 3.13. Test chip CPUID Register bit assignments

Table 3.13 shows the bit assignments.

Table 3.13. Test chip CPUID Register bit assignments
BitsNameFunction
[31:0]-

Cortex-A5 CPU ID


Test chip SCC Registers 0x008-0xFF0

These registers are reserved. You must not attempt to write to or read from them.

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