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Appendix D. Revisions

This appendix describes the technical changes between released issues of this book.

Table D.1. Issue A
ChangeLocationAffects

First release

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Table D.2. Differences between Issue A and Issue B
ChangeLocationAffects
Updated AC characteristics.Table C.1All revisions
Included MMB from FPGA daughterboard as input to IOFPGA on Versatile Express motherboards.MultiMedia Bus (MMB)All revisions
Included MCC in description of signal CB_READY.Table 2.1All revisions
Additional reading section of Preface refers to DSTREAM documents instead of RVI.Additional readingAll revisions

Updated clock names:

SMB output clock.

MMB output clock.

MMB output clock.

Figure 2.8

Figure 2.8

Table B.20

All revisions

Inserted note underneath Figure 2.9 to explain control of polarity of MMB_IDCLK.

Overview of clocks

All revisions
Updated figure to remove AXI RAM block.Figure 2.2All revisions

Shortened Configuration chapter.

Information is now in a new document:

Versatile Express Configuration Technical Reference Manual.

Added other information about custom motherboard.

Configuration architectureAll revisions

Added new documents to Additional Reading section of Preface:

Versatile Express Configuration Technical Reference Manual

Programmer Module (V2M-CP1)

LogicTile Express 13MG Technical Reference Manual.

Additional readingAll revisions

Table D.3. Differences between Issue B and Issue C
ChangeLocationAffects
Updated interrupt description.

Interrupts

Figure 2.10

Table 2.4

All revisions

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