You copied the Doc URL to your clipboard.

2.11. HDLCD

An ARM HDLCD controller in the Cortex-A5 MPCore test chip provides graphic display capabilities. The controller is a frame buffer device that is capable of displaying up to 1920×1080p pixel resolution at 60Hz with a 165MHz pixel clock from OSCCLK3. The MultiMedia Bus (MMB) connects the 24-bit RGB data directly between the test chip and the motherboard through header HDRY. The multiplexer FPGA on the motherboard can select this bus to drive the analog and digital interfaces for the DVI connector.

The HDLCD frame buffer is located in DDR2 memory serviced by the DMC from the test chip bus matrix. This ensures maximum data bandwidth between the Cortex-A5 MPCore cluster, the HDLCD controller, and DDR2 memory without accessing off-chip devices.

Figure 2.16 shows a functional overview of the HDLCD controller and its connections to the Cortex-A5 test chip and the motherboard.

See Appendix B HDLCD controller for a full description of the HDLCD controller.

Figure 2.16. HDLCD graphics system interconnect

Figure 2.16. HDLCD graphics system interconnect

Was this page helpful? Yes No