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3.2. Daughterboard memory map

The CoreTile Express A5x2 daughterboard uses the ARM Cortex-A Series memory map. Figure 3.1 shows the daughterboard memory map.

Figure 3.1. CoreTile Express A5x2 daughterboard memory map

Figure 3.1. CoreTile Express A5x2 daughterboard
memory map

A typical system boots from SMC CS0 that addresses the motherboard NOR flash 0. See Remapping memory. After DDR2 configuration is complete, the exception vectors are moved into the DDR2 area using the CoreSight vector offset registers.

Table 3.1 shows the daughterboard peripheral interfaces.

Table 3.1. Peripheral memory map
Address rangeSizeDescription
0x0000_0000-0x03FF_FFFF64MBCS0-Motherboard NOR flash 0.
0x0800_0000-0x0BFF_FFFF64MBCS0-Motherboard NOR flash 0.
0x0C00_0000-0x0FFF_FFFF64MBCS4-Nor flash 1.
0x1C00_0000-0x1FFF_FFFF64MBCS3-system registers and peripherals.

External AXI master interface.

Remap option.

0x2000_0000-0x2FFF_FFFF256MBTest chip peripherals.
0x3000_0000-0x3FFF_FFFF256MBCortex-A5 Accelerator Coherency Port (ACP)
0x4000_0000-0x7FFF_FFFF1GBExternal AXI between daughterboards.

CoreTile Express A5x2 daughterboard DDR2.

Block 1.


CoreTile Express A5x2 daughterboard DDR2.

Alias to Block 1.

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