To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:
except for the MPU_RASR, it must use aligned word accesses
for the MPU_RASR it can use byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to prevent any previous region settings from affecting the new MPU setup.
Usually, a microcontroller system has only a single processor and no caches. In such a system, program the MPU as follows:
|Memory region||TEX||C||B||S||Memory type and attributes|
|Flash memory||Normal memory, Non-shareable, write-through|
|Internal SRAM||Normal memory, Shareable, write-through|
|External SRAM||Normal memory, Shareable, write-back, write-allocate|
|Peripherals||Device memory, Shareable|
In most microcontroller implementations, the shareability and cache policy attributes do not affect the system behavior. However, using these settings for the MPU regions can make the application code more portable. The values given are for typical situations. In special systems, such as multiprocessor designs or designs with a separate DMA engine, the shareability attribute might be important. In these cases see the recommendations of the memory device manufacturer.