Table A.1 shows the Cortex-M3 implementation options.
|Option||Description, and affected documentation|
|Inclusion of MPU|
The implementer decides whether to include the MPU. See the Optional Memory Protection Unit.
|Number of interrupts|
The implementer decides how many interrupts the Cortex-M3 implementation supports Cortex-M3 implementation supports, in the range 1-240. This affects:
The range of IRQ values in Table 2-5 on page 2-6.
Entries in the last row of Table 2.16, particularly if only one interrupt is implemented.
The maximum interrupt number, and associated information where appropriate, in:
The number of implemented Nested Vectored Interrupt Controller (NVIC) registers in:
|Number of priority bits|
The implementer decides how many priority bits are implemented in priority value fields, in the range 3-8. This affects The maximum priority level value in Nested Vectored Interrupt Controller.
|Inclusion of the WIC|
The implementer decides whether to include the Wakeup interrupt Controller (WIC), see The optional Wakeup Interrupt Controller.
|Sleep mode power-saving|
The implementer decides what sleep modes to implement, and the power-saving measures associated with any implemented mode, See Power management.
Sleep mode power saving might also affect the SysTick behavior, see SysTick usage hints and tips.
|Register reset values|
The implementer decides whether all registers in the register bank can be reset. This affects the reset values, see Table 2.2.
|Endianness||The implementer decides whether the memory system is little-endian or big-endian, see Data types and Memory endianness.|
Some features of the memory system are implementation-specific. This means that the Memory model cannot completely describe the memory map for a specific Cortex-M3 implementation.
The SYST_CALIB register is implementation- defined. This can affect: