You copied the Doc URL to your clipboard.

A.1. Cortex-M4 implementation options

Table A.1 shows the Cortex-M4 implementation options:

Table A.1. Effects of the Cortex-M4 implementation options
Option Description, and affected documentation
Inclusion of MPU

The implementer decides whether to include the Memory Protection Unit (MPU). See the Optional Memory Protection Unit.

Inclusion of FPU

Only the Cortex-M4F includes the Floating Point Unit (FPU). See:

Number of interrupts

The implementer decides how many interrupts the Cortex-M4 implementation supports Cortex-M4 implementation supports, in the range 1-240. This affects:

 

The range of IRQ values in Table 2-5 on page 2-6

Entries in the last row of Table 2.16, particularly if only one interrupt is implemented.

The maximum interrupt number, and associated information where appropriate, in:

The number of implemented Nested Vectored Interrupt Controller (NVIC) registers in:

Vector Table Offset Register, including the figure and Table 4.16. See the configuration information in the section for guidance on the required configuration.

Number of priority bits

The implementer decides how many priority bits are implemented in priority value fields, in the range 3-8. This affects The maximum priority level value in Nested Vectored Interrupt Controller.

Inclusion of the WIC

The implementer decides whether to include the Wakeup interrupt Controller (WIC), see The optional Wakeup Interrupt Controller.

Sleep mode power-saving

The implementer decides what sleep modes to implement, and the power-saving measures associated with any implemented mode, See Power management.

Sleep mode power saving might also affect the SysTick behavior, see SysTick usage hints and tips.

Register reset values

The implementer decides whether all registers in the register bank can be reset. This affects the reset values, see Table 2.2.

Endianness The implementer decides whether the memory system is little-endian or big-endian, see Data typesData types and Memory endianness.
Memory features

Some features of the memory system are implementation-specific. This means that the Memory model cannot completely describe the memory map for a specific Cortex-M4 implementation.

Bit-banding

The implementer decides whether bit-banding is implemented., see Optional bit-banding and Memory model.

SysTick timer

The SYST_CALIB register is implementation- defined. This can affect:


Was this page helpful? Yes No