You copied the Doc URL to your clipboard.

A.2. Fragment processor performance counters

Table A.2 lists Mali GPU performance counters that monitor the fragment processor.

Table A.2. Fragment processor performance counters
Counter NameDescription
Active clock cycles countThe number of clock cycles that were active between polygon start and IRQ.
Bus read request cycles countNumber of cycles the bus read request signal was HIGH.
Bus write request cycles countNumber of cycles of the bus write request signal was HIGH.
Bus read transactions countNumber of read requests accepted by the bus.
Bus write transactions countNumber of write requests accepted by the bus.
Compressed texture cache compressed hit countNumber of texture cache hits for compressed textures.
Compressed texture cache compressed miss countNumber of texture cache misses for compressed textures.
Fragments passed z-stencil countNumber of fragments passing Z and stencil test.
Fragment rasterized countNumber of fragment rasterized. Fragments/(Quads x 4) gives the average actual fragments per quad.
Fragments rejected fragment-kill countNumber of fragments exiting the fragment shader as killed.
Fragments rejected fwd-fragment-kill countNumber of fragments killed by forward fragment kill.
Instruction completed count

Number of fragment shader instruction words completed. This is a function of fragments processed and the length of the shader programs.

The formula for instruction completed count is:

(Number of Quads) x (Number of pixels in a quad) x (instructions in the shader).

Instruction failed load-miss countNumber of fragment shader instructions not completed because of failed load operation.
Instruction failed store-miss countNumber of fragment shader instructions not completed because of failed store operation.
Instruction failed texture-miss countNumber of fragment shader instructions not completed because of failed texture operation.
Instruction failed tile read-miss countNumber of fragment shader instructions not completed because of failed read from the tilebuffer.
Instruction failed varying-miss countNumber of fragment shader instructions not completed because of failed varying operation.
Lines countNumber of lines read from the polygon list.
Load unit readsNumber of 64-bit words read from the bus by the LOAD sub-instruction.
Load/Store cache hit countNumber of hits in the load/store cache.
Load/Store cache miss countNumber of misses in the load/store cache.
Patches evaluatedNumber of patches evaluated for EarlyZ rejection.
Patches rejected early z/stencil countNumber of patches rejected by EarlyZ. A patch can be 8x8, 4x4 or 2x2 fragments.
Pipeline bubbles cycle countNumber of unused cycles in the fragment shader while rendering is active.
Pixel rectangle countNumber of pixel rectangles read from the polygon list.
Points countNumber of points read from the polygon list.
Polygon countNumber of triangles read from the polygon list.
Polygon list readsNumber of 64-bit words read from the bus by the Polygon list reader.
Program cache hit countNumber of hits in the program cache.
Program cache miss countNumber of misses in the program cache.
Program cache readsNumber of 64-bit words read from the bus into the fragment shader program cache.
Quad rasterized countNumber of 2x2 quads output from the rasterizer.
RSW readsNumber of 64-bit words read from the bus into the Render State Word register.
Stall cycles PolygonListReaderNumber of clock cycles Polygon List Reader waited for output being collected.
Stall cycles triangle setupNumber of clock cycles TSC waits for input.
Store unit writesNumber of 64-bit words written to the bus.
Texture cache conflict miss countNumber of times a requested texel was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache.
Texture cache hit countNumber of times a requested texel was found in the texture cache.
Texture cache miss countNumber of times a requested texel was not found in the texture cache.
Texture cache uncompressed readsNumber of 64-bit words read from the bus into the uncompressed textures cache.
Texture descriptor remapping readsNumber of 64-bit words read from the bus when reading from the texture descriptor remapping table.
Texture descriptors readsNumber of 64-bit words containing texture descriptors read from the bus.
Texture mapper cycle countNumber of texture operation cycles.
Texture mapper multipass countNumber of texture operations looped because more texture passes are required.
Tile write-back writesNumber of 64-bit words written to the bus by the write-back unit.
Total bus readsTotal number of 64-bit words read from the bus.
Total bus writesTotal number of 64-bit words written to the bus.
Uniform remapping readsNumber of 64-bit words read from the bus when reading from the uniform remapping table.
Varying cache conflict miss count Number of times a requested varying was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache.
Varying cache hit countNumber of times a requested varying was found in the cache.
Varying cache miss countNumber of times a requested varying was not found in the cache.
Varying readsNumber of 64-bit words containing varyings generated by the vertex processor, read from the bus.
Vertex cache hit countNumber of times a requested vertex was found in the cache.
Vertex cache miss countNumber of times a requested vertex was not found in the cache.
Vertex cache readsNumber of 64-bit words read from the bus into the vertex cache.