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Appendix B. Midgard Architecture Performance Counters

This appendix lists the performance counters for Midgard architecture Mali GPUs.

Table B.1 lists the Midgard architecture Mali GPU performance counters.

Table B.1. Midgard architecture Mali GPU performance counters
Counter NameDescription
Mali Job Manager Cycles
GPU cyclesNumber of cycles the GPU was active
IRQ cyclesNumber of cycles the GPU had a pending interrupt
JS0 cyclesNumber of cycles JS0 (fragment) was active
JS1 cyclesNumber of cycles JS1 (vertex/tiler/compute) was active
JS2 cyclesNumber of cycles JS2 (compute) was active
Mali Job Manager Work
JS0 jobsNumber of Jobs (fragment) completed in JS0
JS0 tasksNumber of Tasks completed in JS0
JS1 jobsNumber of Jobs (vertex/tiler/compute) completed in JS1
JS1 tasksNumber of Tasks completed in JS1
JS2 jobs Number of Jobs (compute) completed in JS2
JS2 tasksNumber of Tasks completed in JS2
Mali Core Cycles
Tripipe cyclesNumber of cycles the Tripipe was active
Fragment cyclesNumber of cycles fragment processing was active
Compute cyclesNumber of cycles vertex\compute processing was active
Fragment cycles waiting for tileNumber of cycles spent waiting for a physical tile buffer
Mali Core Threads
Fragment threadsNumber of fragment threads started
Dummy fragment threadsNumber of dummy fragment threads started
Compute threadsNumber of vertex\compute threads started
Frag threads doing late ZSNumber of threads doing late ZS test
Frag threads killed late ZSNumber of threads killed by late ZS test
Mali Fragment Primitives
Primitives loadedNumber of primitives loaded from tiler
Primitives droppedNumber of primitives dropped because out of tile
Mali Fragment Quads
Quads rasterizedNumber of quads rasterized
Quads doing early ZSNumber of quads doing early ZS test
Quads killed early ZNumber of quads killed by early ZS test
Mali Fragment Tasks
Tiles renderedNumber of tiles rendered
Tile writes killed by TENumber of tile writes skipped by transaction elimination
Mali Arithmetic Pipe
A instructions Number of instructions completed by the A-pipe (normalized per pipeline)
Mali Load/Store Pipe
LS instructionsNumber of instructions completed by the LS-pipe
LS instruction issuesNumber of instructions issued to the LS-pipe, including restarts
Mali Texture Pipe
T instructionsNumber of instructions completed by the T-pipe
T instruction issuesNumber of instructions issued to the T-pipe, including restarts
Cache missesNumber of instructions in the T-pipe, recirculated because of cache miss
Mali Load/Store Cache
Read hitsNumber of read hits in the Load/Store cache
Read missesNumber of read misses in the Load/Store cache
Write hitsNumber of write hits in the Load/Store cache
Write missesNumber of write misses in the Load/Store cache
Atomic hitsNumber of atomic hits in the Load/Store cache
Atomic misses Number of atomic misses in the Load/Store cache
Line fetchesNumber of line fetches in the Load/Store cache
Dirty line evictionsNumber of dirty line evictions in the Load/Store cache
Snoops in to LSCNumber of coherent memory snoops in to the Load/Store cache
Mali L2 Cache
External write beatsNumber of external bus write beats
External read beatsNumber of external bus read beats
Cache read hitsNumber of reads hitting in the L2 cache
Write hitsNumber of writes hitting in the L2 cache
Write snoopsNumber of write transaction snoops
Read snoopsNumber of read transaction snoops
External bus stalls (AR)Number of cycles a valid read address (AR) is stalled by the external interconnect
External bus stalls (W)Number of cycles a valid write data (W channel) is stalled by the external interconnect

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