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Appendix C. Revisions

This appendix describes the technical changes between released issues of this book.

Table C.1. Issue A

No changes, first release


Table C.2. Differences between Issue A and Issue B
Minimum design settings for daughterboard operation section added.Minimum design settings for daughterboard operationAll revisions
Changed note text to accommodate new section mentioned above.Serial Configuration Controller (SCC)All revisions
Changed signal names from nSRST to nRSTREQ.

Figure 2.8

Minimum design settings for daughterboard operation

All revisions

Added note to say that signal nRSTREQ must be tied HIGH when the FPGA design does not support the SCC serial interface.

Serial Configuration Controller (SCC)

All revisions

Reference in main text to tying nSRST HIGH removed.

Serial Configuration Controller (SCC)All revisions
Changed Signals chapter to Appendix to match other documents in the Versatile Express set.Appendix A Signal DescriptionsAll revisions

Table C.3. Differences between Issue B and Issue C

Glossary removed. Reference and link to ARM Glossary inserted.

GlossaryAll revisions

Configuration section shortened.

Information is now in new document ARM® Versatile™ Express Configuration Technical Reference Manual.

FPGA image programming and daughterboard configuration

All revisions

New documents added to Additional Reading section of Preface:

ARM® Versatile™ Express Configuration Technical Reference Manual

ARM® CoreTile Express A5x2 Technical Reference Manual

ARM® CoreTile Express A15x2 Technical Reference Manual.

Additional readingAll revisions
Added speed grade to FPGA descriptions.

About the LogicTile Express 13MG daughterboard

Overview of the daughterboard hardware

All revisions

Table C.4. Differences between Issue C and Issue D
Added matched clock length L.Global clocksAll revisions

Table C.5. Differences between Issue D and Issue E
Corrected Trace Dual and Trace single connector labels.Trace connectorsAll revisions

Table C.6. Differences between Issue E and Issue F
Added table showing daughterboard clock information.Table 2.4All revisions
Added extra information to clock diagram.Figure 2.12All revisions

Table C.7. Differences between Issue F and Issue G
Corrected description of PCI-Express system.

Overview of system interconnect

PCI-Express Bus (PCIe)

Figure 2.12

All revisions

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