The SCC serial interface operates at 0.5MHz. The serial interface is similar to a memory-mapped peripheral because it has an address and a data phase. Figure 2.10 and Figure 2.11 show the timing diagrams for write and read operations respectively. The SCC operates a 12-bit address and 32-bit data phase.
The nCFGRST output from the Daughterboard Configuration Controller loads the default configuration settings into the FPGA. CFGLOAD determines when WRITE DATA is completed, or when READ DATA is expected to be ready. The Daughterboard Configuration Controller provides CFGCLK to the FPGA. CFGWnR changes depending on the access type.
WRITE DATA is sent Most Significant Bit (MSB) first.
READ DATA is received Least Significant Bit (LSB) first.
The SCC also has an Advanced Peripheral Bus (APB) interface that you can use to access the internal registers.
If the SCC serial interface is not implemented in the FPGA design, ARM recommends that you tie off the CFGDATAOUT and nRSTREQ signals.
You must tie the CFGDATAOUT signal from both FPGAs LOW. These are the NAND_D pins on each FPGA.
You must tie the nRSTREQ signal from both FPGAs HIGH. These are the NAND_D pins on each FPGA.
Figure 2.10 shows the timing diagram for the write operation.
Figure 2.11 shows the timing diagram for the read operation.
Table 2.3 shows the Daughterboard Configuration Controller AC timing requirements.
|Daughterboard Configuration Controller output valid time, DCCTov||1μs|
|Daughterboard Configuration Controller output hold time, DCCToh||1μs|
|Daughterboard Configuration Controller input setup time, DCCTis||1μs|
|Daughterboard Configuration Controller input hold time, DCCTih||1μs|