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2.3.3. Resets

The MCC on the motherboard controls the daughterboard reset signals. Figure 2.8 shows the reset request signals from the daughterboard, and the reset signals from the motherboard.

Reset requests from the daughterboard can originate in FPGA 1, FPGA 2, or from the P-JTAG connector.

A reset request from the P-JTAG connector can connect to CB_RSTREQ through FPGA 2 and Daughterboard Configuration Controller 2.

A reset request from either FPGA can connect to CB_RSTREQ through its associated Daughterboard Configuration Controller.

The reset request from the daughterboard results in the motherboard asserting CB_nRST. CB_nPOR can optionally be asserted by the setting ASSERTNPOR, that can be either TRUE or FALSE in the config.txt motherboard configuration file. See the ARM® Versatile™ Express Configuration Technical Reference Manual for an example config.txt file.


Only the CB_nPOR and CB_nRST signals are driven to the daughterboard FPGAs and Daughterboard Configuration Controllers. CB_RSTREQ can be driven from the FPGA through the Daughterboard Configuration Controller to request a cold or warm reset, depending on the motherboard configuration file settings.

Figure 2.8. Daughterboard resets

Figure 2.8. Daughterboard resets

Figure 2.9 shows the basic power-up reset cycle.

Figure 2.9. Reset timing cycle

Figure 2.9. Reset timing cycle

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