The hardware infrastructure supports system expansion and a number of debug interfaces. Figure 2.1 shows the high-level hardware infrastructure. For information on the connector signals to these additional interfaces, see Appendix A Signal Descriptions.
The configuration images loaded into the two FPGAs at power-up define the functionality of the daughterboard. Application note AN233, LogicTile Express 13MG example design for a CoreTile Express A9x4, provided by ARM, implements an example AMBA 3.0 system using the daughterboard.
The hardware infrastructure of the daughterboard comprises:
Two Xilinx Virtex-6 FPGAs:
XC6VLX550T, FPGA 1, 5.5 million gates, Gigabit transceiver connection to SATA and HSSTP connectors, speed grade -1.
XC6VLX760, FPGA 2, 7.6 million gates, speed-grade -1.
Two NAND Flash memories, one for each FPGA, used to store FPGA images.
A configuration EEPROM that is used to store the board Hardware Board International (HBI) number and names of the current FPGA images.
Two local Daughterboard Configuration Controllers, one for each FPGA, whose purpose is to:
Set the oscillator frequencies.
Set and monitor the power supply voltages.
Load the FPGA images.
Transfer SCC register values.
16MB of on-board ZBT RAM:
Two independent banks of 8MB RAM that is driven by FPGA 2.
SO-DIMM memory connector:
4GB of external DDR2 RAM fitted in the SO-DIMM connector that is driven by FPGA 1.
One header connector, HDRXL, on the bottom side of the board for routing High-Speed Buses (HSBs) from FPGA 2 to the other daughterboard site on the motherboard:
One High-Speed Bus Master, M, interface implemented on FPGA 2.
One High-Speed Bus Slave, S, interface implemented on FPGA 2.
Low Voltage Differential Signaling (LVDS) support, 160 pairs.
20 single-ended signals.
One header connector, HDRYL, for routing buses to the motherboard:
MultiMedia Bus (MMB).
PCI-Express Bus (PCIe).
System Bus (SB).
Static Memory Bus (SMB).
Configuration Bus (CB).
An HSB link between the two FPGAs.
A Master, M, interface and a HSB slave, S, implemented on each FPGA.
LVDS support, 292 single-ended signals that you can configure as up to 146 pairs.
Two header connectors, HDRXU and HDRYU, on the top side of the board to support upward expansion:
320 single-ended IO pins that you can configure as up to 160 pairs, LVDS, and 20 single-ended IO only pins available on FPGA 2 that connect to HDRXU.
182 general, single-ended, IO pins available on FPGA 1 that connect to HDRYU.
Serial Advanced Technology Attachment (SATA) connectors:
One Host, H, connector.
One Device, D, connector.
Two transmit and two receive lanes in each direction.
PCI-Express Bus, PCIe:
PCIe endpoint capability a maximum 8 lanes upwards and downwards.
P-JTAG port for RealView® ICE (RVI) or other compatible third-party debuggers.
Integrated Logic Analyzer (ILA) F-JTAG port for ChipScope, for example.
Two trace ports supporting up to 32-bit trace.
High Speed Serial Trace Port (HSSTP) for prototyping of high-speed trace.
Two green FPGA DONE_LEDs, one for each FPGA indicating FPGA configured.
Two red OverTemp LEDs, one for each FPGA.
18 green general purpose user LEDs, one LED connected directly to each FPGA, and eight LEDs connected to each Daughterboard Configuration Controller.
Eight general-purpose Dual In-Line Package (DIP) switches that are connected to both Daughterboard Configuration Controllers.
A battery to provide power to both FPGAs, to store FPGA image AES decryption keys.
Six on-board programmable oscillators:
Three input to FPGA 1.
Three input to FPGA 2.
For more information, see System interconnect.