Most simulators support the use of assertions in RTL, and enable you to configure the simulator appropriately using command variables that define the available assertion options. These can include:
suppress or enable assertion warnings
select assertion report messages to display
set a minimum severity level for which assertion report messages are output
set a minimum severity level for which an assertion causes the simulator to stop.
The protocol checkers are written using SystemVerilog version IEEE 1800-2005, and are tested with a number of simulators. Contact your simulator supplier and see your documentation for more information on using SystemVerilog Assertions.